microblaze.vhd

Xilinx软核microblaze源码(VHDL)版本7.10

    generic (
      C_DPLB_WIDTH          : natural;
      C_DELAYED_DATA_STROBE : boolean;
      C_OUTPUT_DFFS         : boolean
      );
    port (
      -- global signals
      Clk   : in std_logic;
      Reset : in std_logic;

      -- PLB signals
      DPLB_M_ABort      : out std_logic;
      DPLB_M_ABus       : out std_logic_vector(0 to 31);
      DPLB_M_UABus      : out std_logic_vector(0 to 31);
      DPLB_M_BE         : out std_logic_vector(0 to (C_DPLB_DWIDTH-1)/8);
      DPLB_M_busLock    : out std_logic;
      DPLB_M_lockErr    : out std_logic;
      DPLB_M_MSize      : out std_logic_vector(0 to 1);
      DPLB_M_priority   : out std_logic_vector(0 to 1);
      DPLB_M_rdBurst    : out std_logic;
      DPLB_M_request    : out std_logic;
      DPLB_M_RNW        : out std_logic;
      DPLB_M_size       : out std_logic_vector(0 to 3);
      DPLB_M_TAttribute : out std_logic_vector(0 to 15);
      DPLB_M_type       : out std_logic_vector(0 to 2);
      DPLB_M_wrBurst    : out std_logic;
      DPLB_M_wrDBus     : out std_logic_vector(0 to C_DPLB_DWIDTH-1);

      DPLB_MBusy        : in std_logic;
      DPLB_MRdErr       : in std_logic;
      DPLB_MWrErr       : in std_logic;
      DPLB_MIRQ         : in std_logic;
      DPLB_MWrBTerm     : in std_logic;
      DPLB_MWrDAck      : in std_logic;
      DPLB_MAddrAck     : in std_logic;
      DPLB_MRdBTerm     : in std_logic;
      DPLB_MRdDAck      : in std_logic;
      DPLB_MRdDBus      : in std_logic_vector(0 to C_DPLB_DWIDTH-1);
      DPLB_MRdWdAddr    : in std_logic_vector(0 to 3);
      DPLB_MRearbitrate : in std_logic;
      DPLB_MSSize       : in std_logic_vector(0 to 1);
      DPLB_MTimeout     : in std_logic;

      -- Local Bus signals
      MEM_DataBus_Access      : in std_logic;
      MEM_DataBus_Addr        : in DATA_TYPE;
      MEM_DataBus_Write       : in std_logic;
      MEM_DataBus_Write_Data  : in DATA_TYPE;
      MEM_DataBus_Byte_Enable : in DATA_BE_TYPE;
      MEM_DataBus_Read        : in std_logic;

      WB_DPLB_Data_Strobe : out std_logic;
      WB_DPLB_Read_Data   : out DATA_TYPE;

      -- other signals
      MEM_DataBus_Drop_Request   : in  std_logic;
      MEM_DataBus_Enable_BusLock : in  std_logic;
      MEM_DPLB_Data_Strobe       : out std_logic;
      MEM_DPLB_Exception         : out std_logic);
  end component DPLB_Interface;

  component DOPB_Interface is
    generic (
      C_OPB_WIDTH           : natural;
      C_DELAYED_DATA_STROBE : boolean
      );
    port (
      -- global signals
      Clk   : in std_logic;
      Reset : in std_logic;

      -- OPB signals
      DM_ABus      : out std_logic_vector(0 to C_OPB_WIDTH-1);
      DM_BE        : out std_logic_vector(0 to (C_OPB_WIDTH-1)/8);
      DM_busLock   : out std_logic;
      DM_DBus      : out std_logic_vector(0 to C_OPB_WIDTH-1);
      DM_request   : out std_logic;
      DM_RNW       : out std_logic;
      DM_select    : out std_logic;
      DM_seqAddr   : out std_logic;
      DOPB_DBus    : in  std_logic_vector(0 to C_OPB_WIDTH-1);
      DOPB_errAck  : in  std_logic;
      DOPB_MGrant  : in  std_logic;
      DOPB_retry   : in  std_logic;
      DOPB_timeout : in  std_logic;
      DOPB_xferAck : in  std_logic;

      -- Local Bus signals
      MEM_DataBus_Access      : in std_logic;
      MEM_DataBus_Addr        : in DATA_TYPE;
      MEM_DataBus_Write       : in std_logic;
      MEM_DataBus_Write_Data  : in DATA_TYPE;
      MEM_DataBus_Byte_Enable : in DATA_BE_TYPE;
      MEM_DataBus_Read        : in std_logic;

      WB_DOPB_Data_Strobe : out std_logic;
      WB_DOPB_Read_Data   : out DATA_TYPE;

      -- other signals
      MEM_DataBus_Drop_Request   : in  std_logic;
      MEM_DataBus_Enable_BusLock : in  std_logic;
      MEM_DOPB_Data_Strobe       : out std_logic;
      MEM_DOPB_Exception         : out std_logic);
  end component DOPB_Interface;

  component IPLB_Interface is
    generic (
      C_IPLB_DWIDTH : natural);
    port (
      -- global signals
      Clk   : in std_logic;
      Reset : in std_logic;

      -- PLB signals
      IPLB_M_ABort      : out std_logic;
      IPLB_M_ABus       : out std_logic_vector(0 to 31);
      IPLB_M_UABus      : out std_logic_vector(0 to 31);
      IPLB_M_BE         : out std_logic_vector(0 to (C_IPLB_DWIDTH-1)/8);
      IPLB_M_busLock    : out std_logic;
      IPLB_M_lockErr    : out std_logic;
      IPLB_M_MSize      : out std_logic_vector(0 to 1);
      IPLB_M_priority   : out std_logic_vector(0 to 1);
      IPLB_M_rdBurst    : out std_logic;
      IPLB_M_request    : out std_logic;
      IPLB_M_RNW        : out std_logic;
      IPLB_M_size       : out std_logic_vector(0 to 3);
      IPLB_M_TAttribute : out std_logic_vector(0 to 15);
      IPLB_M_type       : out std_logic_vector(0 to 2);
      IPLB_M_wrBurst    : out std_logic;
      IPLB_M_wrDBus     : out std_logic_vector(0 to C_IPLB_DWIDTH-1);
      IPLB_MBusy        : in  std_logic;
      IPLB_MRdErr       : in  std_logic;
      IPLB_MWrErr       : in  std_logic;
      IPLB_MIRQ         : in  std_logic;
      IPLB_MWrBTerm     : in  std_logic;
      IPLB_MWrDAck      : in  std_logic;
      IPLB_MAddrAck     : in  std_logic;
      IPLB_MRdBTerm     : in  std_logic;
      IPLB_MRdDAck      : in  std_logic;
      IPLB_MRdDBus      : in  std_logic_vector(0 to C_IPLB_DWIDTH-1);
      IPLB_MRdWdAddr    : in  std_logic_vector(0 to 3);
      IPLB_MRearbitrate : in  std_logic;
      IPLB_MSSize       : in  std_logic_vector(0 to 1);
      IPLB_MTimeout     : in  std_logic;

      -- Local Bus signals
      IPLB_Data_Strobe  : out std_logic;
      IPLB_Data         : out DATA_TYPE;
      IB_Addr           : in  DATA_TYPE;
      IB_Addr_Strobe    : in  std_logic;
      IB_Fetch          : in  std_logic;
      IPLB_Drop_Request : in  std_logic;

      -- other signals
      IPLB_Exception : out std_logic);
  end component IPLB_Interface;
  
  component IOPB_Interface is
    generic (
      C_OPB_WIDTH : natural);
    port (
      -- global signals
      Clk   : in std_logic;
      Reset : in std_logic;

      -- OPB signals
      IM_ABus      : out std_logic_vector(0 to C_OPB_WIDTH-1);
      IM_BE        : out std_logic_vector(0 to (C_OPB_WIDTH-1)/8);
      IM_busLock   : out std_logic;
      IM_request   : out std_logic;
      IM_select    : out std_logic;
      IM_seqAddr   : out std_logic;
      IM_DBus      : out std_logic_vector(0 to C_OPB_WIDTH-1);
      IM_RNW       : out std_logic;
      IOPB_DBus    : in  std_logic_vector(0 to C_OPB_WIDTH-1);
      IOPB_errAck  : in  std_logic;
      IOPB_MGrant  : in  std_logic;
      IOPB_retry   : in  std_logic;
      IOPB_timeout : in  std_logic;
      IOPB_xferAck : in  std_logic;

      -- Local Bus signals
      IOPB_Data_Strobe  : out std_logic;
      IOPB_Data         : out DATA_TYPE;
      IB_Addr           : in  DATA_TYPE;
      IB_Addr_Strobe    : in  std_logic;
      IB_Fetch          : in  std_logic;
      IOPB_Drop_Request : in  std_logic;

      -- other signals
      IOPB_Exception : out std_logic
      );
  end component IOPB_Interface;

  -----------------------------------------------------------------------------
  -----------------------------------------------------------------------------
  -- Component declarations for area optimized version
  -----------------------------------------------------------------------------
  -----------------------------------------------------------------------------

  component DCache is
    generic (
      C_D_Ext              : boolean;
      C_OPB_WIDTH          : natural;
      C_DATA_SIZE          : natural;
      C_TARGET             : TARGET_FAMILY_TYPE;
      C_DCACHE_BASEADDR    : std_logic_vector(0 to 31) := X"00000000";
      C_DCACHE_HIGHADDR    : std_logic_vector(0 to 31) := X"3FFFFFFF";
      C_CACHELINE_SIZE     : natural                   := 4;
      C_ALLOW_DCACHE_WR    : integer;
      C_ADDR_TAG_BITS      : natural;
      C_CACHE_BYTE_SIZE    : natural;
      C_DCACHE_ALWAYS_USED : integer
      );
    port (
      -- global signals
      Clk   : in std_logic;
      Reset : in boolean;

      -- Local Bus signals
      Data_Addr           : in  std_logic_vector(0 to C_DATA_SIZE-1);
      D_AS                : in  std_logic;
      Data_Write          : in  std_logic_vector(0 to 31);
      Data_Read           : out std_logic_vector(0 to 31);
      DReady              : out std_logic;
      Read_Strobe         : in  std_logic;
      Write_Strobe        : in  std_logic;
      Byte_Enable         : in  std_logic_vector(0 to 3);
      Read_Strobe_No_Dbg  : in  std_logic;
      Write_Strobe_No_Dbg : in  std_logic;
      Byte                : in  boolean;
      Doublet             : in  boolean;

      -- Externat Data bus signals
      DExt_Data_Read : in std_logic_vector(0 to C_DATA_SIZE-1);
      DExt_DReady    : in std_logic;

      -- Combine DLMB and DExt ready signal
      Combined_Dready : in std_logic;

      -- Control signals
      DCache_Enabled : in boolean;
      Op1            : in std_logic_vector(0 to C_OPB_WIDTH-1);
      Op2            : in std_logic_vector(0 to C_OPB_WIDTH-1);
      Write_DCache   : in boolean;

      -- Trace signals
      Trace_Cache_Req : out std_logic;
      Trace_Cache_Hit : out std_logic;

      Valid_Dcache_Access : out std_logic;
      DCache_Read_Idle    : out boolean;

      -- FSL signals
      DCACHE_FSL_IN_Clk     : out std_logic;
      DCACHE_FSL_IN_Read    : out std_logic;
      DCACHE_FSL_IN_Data    : in  std_logic_vector(0 to 31);
      DCACHE_FSL_IN_Control : in  std_logic;
      DCACHE_FSL_IN_Exists  : in  std_logic;

      DCACHE_FSL_OUT_Clk     : out std_logic;
      DCACHE_FSL_OUT_Write   : out std_logic;
      DCACHE_FSL_OUT_Data    : out std_logic_vector(0 to 31);
      DCACHE_FSL_OUT_Control : out std_logic;
      DCACHE_FSL_OUT_Full    : in  std_logic
      );
  end component DCache;

  component ICache is
    generic (
      C_DEBUG_ENABLED      : integer                   := 1;
      C_OPB_WIDTH          : natural;
      C_DATA_SIZE          : natural;
      C_TARGET             : TARGET_FAMILY_TYPE;
      C_ICACHE_BASEADDR    : std_logic_vector(0 to 31) := X"00000000";
      C_ICACHE_HIGHADDR    : std_logic_vector(0 to 31) := X"3FFFFFFF";
      C_CACHELINE_SIZE     : natural                   := 4;
      C_ALLOW_ICACHE_WR    : integer;
      C_ADDR_TAG_BITS      : natural;
      C_CACHE_BYTE_SIZE    : natural;
      C_ICACHE_ALWAYS_USED : integer
      );
    port (
      -- global signals
      Clk   : in std_logic;
      Reset : in boolean;

      -- Local Bus signals
      Instr_Addr : in  std_logic_vector(0 to C_DATA_SIZE-1);
      I_AS       : in  std_logic;
      Instr      : out std_logic_vector(0 to 31);
      IReady     : out std_logic;

      -- Combined Iready from all other sources for instruction fetch
      Combined_IReady : in std_logic;

      -- Control signals
      ICache_Enabled : in boolean;
      Op1            : in std_logic_vector(0 to C_OPB_WIDTH-1);
      Op2            : in std_logic_vector(0 to C_OPB_WIDTH-1);
      Write_ICache   : in boolean;

      -- Trace signals
      Trace_Cache_Req : out std_logic;
      Trace_Cache_Hit : out std_logic;

      Valid_ICache_Access : out std_logic;
      ICache_Read_Idle    : out boolean;

      -- FSL signals
      ICACHE_FSL_IN_Clk     : out std_logic;
      ICACHE_FSL_IN_Read    : out std_logic;
      ICACHE_FSL_IN_Data    : in  std_logic_vector(0 to 31);
      ICACHE_FSL_IN_Control : in  std_logic;
      ICACHE_FSL_IN_Exists  : in  std_logic;

      ICACHE_FSL_OUT_Clk     : out std_logic;
      ICACHE_FSL_OUT_Write   : out std_logic;
      ICACHE_FSL_OUT_Data    : out std_logic_vector(0 to 31);
      ICACHE_FSL_OUT_Control : out std_logic;
      ICACHE_FSL_OUT_Full    : in  std_logic
      );
  end component ICache;

  component Decode is
    generic (