microblaze.vhd

Xilinx软核microblaze源码(VHDL)版本7.10

    Trace_Instruction      : out std_logic_vector(0 to C_DATA_SIZE-1);
    Trace_Valid_Instr      : out std_logic;
    Trace_PC               : out std_logic_vector(0 to C_DATA_SIZE-1);
    Trace_Reg_Write        : out std_logic;
    Trace_Reg_Addr         : out std_logic_vector(0 to 4);
    Trace_MSR_Reg          : out std_logic_vector(0 to 14);
    Trace_PID_Reg          : out std_logic_vector(0 to 7);
    Trace_New_Reg_Value    : out std_logic_vector(0 to C_DATA_SIZE-1);
    Trace_Exception_Taken  : out std_logic;
    Trace_Exception_Kind   : out std_logic_vector(0 to 4);
    Trace_Jump_Taken       : out std_logic;
    Trace_Delay_Slot       : out std_logic;
    Trace_Data_Address     : out std_logic_vector(0 to C_DATA_SIZE-1);
    Trace_Data_Write_Value : out std_logic_vector(0 to C_DATA_SIZE-1);
    Trace_Data_Byte_Enable : out std_logic_vector(0 to 3);
    Trace_Data_Access      : out std_logic;
    Trace_Data_Read        : out std_logic;
    Trace_Data_Write       : out std_logic;
    Trace_DCache_Req       : out std_logic;
    Trace_DCache_Hit       : out std_logic;
    Trace_ICache_Req       : out std_logic;
    Trace_ICache_Hit       : out std_logic;
    Trace_OF_PipeRun       : out std_logic;
    Trace_EX_PipeRun       : out std_logic;
    Trace_MEM_PipeRun      : out std_logic;
    Trace_MB_Halted        : out std_logic;

    -- FSL signals
    FSL0_S_Clk     : out std_logic;
    FSL0_S_Read    : out std_logic;
    FSL0_S_Data    : in  std_logic_vector(0 to C_FSL_DATA_SIZE-1);
    FSL0_S_Control : in  std_logic;
    FSL0_S_Exists  : in  std_logic;

    FSL1_S_Clk     : out std_logic;
    FSL1_S_Read    : out std_logic;
    FSL1_S_Data    : in  std_logic_vector(0 to C_FSL_DATA_SIZE-1);
    FSL1_S_Control : in  std_logic;
    FSL1_S_Exists  : in  std_logic;

    FSL2_S_Clk     : out std_logic;
    FSL2_S_Read    : out std_logic;
    FSL2_S_Data    : in  std_logic_vector(0 to C_FSL_DATA_SIZE-1);
    FSL2_S_Control : in  std_logic;
    FSL2_S_Exists  : in  std_logic;

    FSL3_S_Clk     : out std_logic;
    FSL3_S_Read    : out std_logic;
    FSL3_S_Data    : in  std_logic_vector(0 to C_FSL_DATA_SIZE-1);
    FSL3_S_Control : in  std_logic;
    FSL3_S_Exists  : in  std_logic;

    FSL4_S_Clk     : out std_logic;
    FSL4_S_Read    : out std_logic;
    FSL4_S_Data    : in  std_logic_vector(0 to C_FSL_DATA_SIZE-1);
    FSL4_S_Control : in  std_logic;
    FSL4_S_Exists  : in  std_logic;

    FSL5_S_Clk     : out std_logic;
    FSL5_S_Read    : out std_logic;
    FSL5_S_Data    : in  std_logic_vector(0 to C_FSL_DATA_SIZE-1);
    FSL5_S_Control : in  std_logic;
    FSL5_S_Exists  : in  std_logic;

    FSL6_S_Clk     : out std_logic;
    FSL6_S_Read    : out std_logic;
    FSL6_S_Data    : in  std_logic_vector(0 to C_FSL_DATA_SIZE-1);
    FSL6_S_Control : in  std_logic;
    FSL6_S_Exists  : in  std_logic;

    FSL7_S_Clk     : out std_logic;
    FSL7_S_Read    : out std_logic;
    FSL7_S_Data    : in  std_logic_vector(0 to C_FSL_DATA_SIZE-1);
    FSL7_S_Control : in  std_logic;
    FSL7_S_Exists  : in  std_logic;

    FSL8_S_Clk     : out std_logic;
    FSL8_S_Read    : out std_logic;
    FSL8_S_Data    : in  std_logic_vector(0 to C_FSL_DATA_SIZE-1);
    FSL8_S_Control : in  std_logic;
    FSL8_S_Exists  : in  std_logic;

    FSL9_S_Clk     : out std_logic;
    FSL9_S_Read    : out std_logic;
    FSL9_S_Data    : in  std_logic_vector(0 to C_FSL_DATA_SIZE-1);
    FSL9_S_Control : in  std_logic;
    FSL9_S_Exists  : in  std_logic;

    FSL10_S_Clk    : out std_logic;
    FSL10_S_Read   : out std_logic;
    FSL10_S_Data   : in  std_logic_vector(0 to C_FSL_DATA_SIZE-1);
    FSL10_S_Control: in  std_logic;
    FSL10_S_Exists : in  std_logic;

    FSL11_S_Clk    : out std_logic;
    FSL11_S_Read   : out std_logic;
    FSL11_S_Data   : in  std_logic_vector(0 to C_FSL_DATA_SIZE-1);
    FSL11_S_Control: in  std_logic;
    FSL11_S_Exists : in  std_logic;

    FSL12_S_Clk    : out std_logic;
    FSL12_S_Read   : out std_logic;
    FSL12_S_Data   : in  std_logic_vector(0 to C_FSL_DATA_SIZE-1);
    FSL12_S_Control: in  std_logic;
    FSL12_S_Exists : in  std_logic;

    FSL13_S_Clk    : out std_logic;
    FSL13_S_Read   : out std_logic;
    FSL13_S_Data   : in  std_logic_vector(0 to C_FSL_DATA_SIZE-1);
    FSL13_S_Control: in  std_logic;
    FSL13_S_Exists : in  std_logic;

    FSL14_S_Clk    : out std_logic;
    FSL14_S_Read   : out std_logic;
    FSL14_S_Data   : in  std_logic_vector(0 to C_FSL_DATA_SIZE-1);
    FSL14_S_Control: in  std_logic;
    FSL14_S_Exists : in  std_logic;

    FSL15_S_Clk    : out std_logic;
    FSL15_S_Read   : out std_logic;
    FSL15_S_Data   : in  std_logic_vector(0 to C_FSL_DATA_SIZE-1);
    FSL15_S_Control: in  std_logic;
    FSL15_S_Exists : in  std_logic;

    FSL0_M_Clk     : out std_logic;
    FSL0_M_Write   : out std_logic;
    FSL0_M_Data    : out std_logic_vector(0 to C_FSL_DATA_SIZE-1);
    FSL0_M_Control : out std_logic;
    FSL0_M_Full    : in  std_logic;

    FSL1_M_Clk     : out std_logic;
    FSL1_M_Write   : out std_logic;
    FSL1_M_Data    : out std_logic_vector(0 to C_FSL_DATA_SIZE-1);
    FSL1_M_Control : out std_logic;
    FSL1_M_Full    : in  std_logic;

    FSL2_M_Clk     : out std_logic;
    FSL2_M_Write   : out std_logic;
    FSL2_M_Data    : out std_logic_vector(0 to C_FSL_DATA_SIZE-1);
    FSL2_M_Control : out std_logic;
    FSL2_M_Full    : in  std_logic;

    FSL3_M_Clk     : out std_logic;
    FSL3_M_Write   : out std_logic;
    FSL3_M_Data    : out std_logic_vector(0 to C_FSL_DATA_SIZE-1);
    FSL3_M_Control : out std_logic;
    FSL3_M_Full    : in  std_logic;

    FSL4_M_Clk     : out std_logic;
    FSL4_M_Write   : out std_logic;
    FSL4_M_Data    : out std_logic_vector(0 to C_FSL_DATA_SIZE-1);
    FSL4_M_Control : out std_logic;
    FSL4_M_Full    : in  std_logic;

    FSL5_M_Clk     : out std_logic;
    FSL5_M_Write   : out std_logic;
    FSL5_M_Data    : out std_logic_vector(0 to C_FSL_DATA_SIZE-1);
    FSL5_M_Control : out std_logic;
    FSL5_M_Full    : in  std_logic;

    FSL6_M_Clk     : out std_logic;
    FSL6_M_Write   : out std_logic;
    FSL6_M_Data    : out std_logic_vector(0 to C_FSL_DATA_SIZE-1);
    FSL6_M_Control : out std_logic;
    FSL6_M_Full    : in  std_logic;

    FSL7_M_Clk     : out std_logic;
    FSL7_M_Write   : out std_logic;
    FSL7_M_Data    : out std_logic_vector(0 to C_FSL_DATA_SIZE-1);
    FSL7_M_Control : out std_logic;
    FSL7_M_Full    : in  std_logic;

    FSL8_M_Clk     : out std_logic;
    FSL8_M_Write   : out std_logic;
    FSL8_M_Data    : out std_logic_vector(0 to C_FSL_DATA_SIZE-1);
    FSL8_M_Control : out std_logic;
    FSL8_M_Full    : in  std_logic;

    FSL9_M_Clk     : out std_logic;
    FSL9_M_Write   : out std_logic;
    FSL9_M_Data    : out std_logic_vector(0 to C_FSL_DATA_SIZE-1);
    FSL9_M_Control : out std_logic;
    FSL9_M_Full    : in  std_logic;

    FSL10_M_Clk     : out std_logic;
    FSL10_M_Write   : out std_logic;
    FSL10_M_Data    : out std_logic_vector(0 to C_FSL_DATA_SIZE-1);
    FSL10_M_Control : out std_logic;
    FSL10_M_Full    : in  std_logic;

    FSL11_M_Clk     : out std_logic;
    FSL11_M_Write   : out std_logic;
    FSL11_M_Data    : out std_logic_vector(0 to C_FSL_DATA_SIZE-1);
    FSL11_M_Control : out std_logic;
    FSL11_M_Full    : in  std_logic;

    FSL12_M_Clk     : out std_logic;
    FSL12_M_Write   : out std_logic;
    FSL12_M_Data    : out std_logic_vector(0 to C_FSL_DATA_SIZE-1);
    FSL12_M_Control : out std_logic;
    FSL12_M_Full    : in  std_logic;

    FSL13_M_Clk     : out std_logic;
    FSL13_M_Write   : out std_logic;
    FSL13_M_Data    : out std_logic_vector(0 to C_FSL_DATA_SIZE-1);
    FSL13_M_Control : out std_logic;
    FSL13_M_Full    : in  std_logic;

    FSL14_M_Clk     : out std_logic;
    FSL14_M_Write   : out std_logic;
    FSL14_M_Data    : out std_logic_vector(0 to C_FSL_DATA_SIZE-1);
    FSL14_M_Control : out std_logic;
    FSL14_M_Full    : in  std_logic;

    FSL15_M_Clk     : out std_logic;
    FSL15_M_Write   : out std_logic;
    FSL15_M_Data    : out std_logic_vector(0 to C_FSL_DATA_SIZE-1);
    FSL15_M_Control : out std_logic;
    FSL15_M_Full    : in  std_logic;

    ICACHE_FSL_IN_Clk     : out std_logic;
    ICACHE_FSL_IN_Read    : out std_logic;
    ICACHE_FSL_IN_Data    : in  std_logic_vector(0 to 31);
    ICACHE_FSL_IN_Control : in  std_logic;
    ICACHE_FSL_IN_Exists  : in  std_logic;

    ICACHE_FSL_OUT_Clk     : out std_logic;
    ICACHE_FSL_OUT_Write   : out std_logic;
    ICACHE_FSL_OUT_Data    : out std_logic_vector(0 to 31);
    ICACHE_FSL_OUT_Control : out std_logic;
    ICACHE_FSL_OUT_Full    : in  std_logic;

    DCACHE_FSL_IN_Clk     : out std_logic;
    DCACHE_FSL_IN_Read    : out std_logic;
    DCACHE_FSL_IN_Data    : in  std_logic_vector(0 to 31);
    DCACHE_FSL_IN_Control : in  std_logic;
    DCACHE_FSL_IN_Exists  : in  std_logic;

    DCACHE_FSL_OUT_Clk     : out std_logic;
    DCACHE_FSL_OUT_Write   : out std_logic;
    DCACHE_FSL_OUT_Data    : out std_logic_vector(0 to 31);
    DCACHE_FSL_OUT_Control : out std_logic;
    DCACHE_FSL_OUT_Full    : in  std_logic
    );
end entity MicroBlaze;

-------------------------------------------------------------------------------
-- Architecture section
-------------------------------------------------------------------------------

library Microblaze_v7_10_a;
use Microblaze_v7_10_a.MicroBlaze_Types.all;

architecture IMP of MicroBlaze is

  -----------------------------------------------------------------------------
  -- Constant declarations
  -----------------------------------------------------------------------------
  constant DEBUG_U_SET     : string := C_INSTANCE;
  constant DECODE_U_SET    : string := C_INSTANCE;
  constant DATA_FLOW_U_SET : string := C_INSTANCE;
  constant DOPB_INTF_U_SET : string := C_INSTANCE;
  constant IOPB_INTF_U_SET : string := C_INSTANCE;

  constant C_DETECT_OPCODE_0x0 : boolean := (C_OPCODE_0x0_ILLEGAL /= 0);
  constant C_MAX_FSL_LINKS     : integer := 16;

  constant SELECT_RTL : boolean            := C_SCO = 1;
  constant TARGET     : TARGET_FAMILY_TYPE := String_To_Family(C_FAMILY, SELECT_RTL);

  constant AREA_OPTIMIZED : boolean := (C_AREA_OPTIMIZED /= 0);

  constant USE_I_OPB       : boolean := (C_I_OPB /= 0);
  constant USE_I_PLB       : boolean := (C_I_PLB /= 0);
  constant USE_I_LMB       : boolean := (C_I_LMB /= 0);
  constant USE_ICACHE      : boolean := (C_USE_ICACHE /= 0);
  constant ALLOW_ICACHE_WR : boolean := (C_ALLOW_ICACHE_WR /= 0);
  constant USE_D_PLB       : boolean := (C_D_PLB /= 0);
  constant USE_D_OPB       : boolean := (C_D_OPB /= 0);
  constant USE_D_LMB       : boolean := (C_D_LMB /= 0);
  constant USE_DOPB_and_NOT_DPLB : boolean := USE_D_OPB and not USE_D_PLB;
  constant USE_D_Ext      : boolean := USE_D_OPB or USE_D_PLB;
  
  constant USE_DCACHE      : boolean := (C_USE_DCACHE /= 0);
  constant ALLOW_DCACHE_WR : boolean := (C_ALLOW_DCACHE_WR /= 0);
  constant USE_BARREL      : boolean := (C_USE_BARREL /= 0);
  constant USE_DIV         : boolean := (C_USE_DIV /= 0);
  constant USE_MSR_INSTR   : boolean := (C_USE_MSR_INSTR /= 0); --or (C_AREA_OPTIMIZED = 0);
  constant USE_PCMP_INSTR : boolean := (C_USE_PCMP_INSTR /= 0); --or (C_AREA_OPTIMIZED = 0);

  constant DEBUG_ENABLED        : boolean := (C_DEBUG_ENABLED /= 0);
  constant UNALIGNED_EXCEPTIONS : boolean := (C_UNALIGNED_EXCEPTIONS /= 0);
  constant ILL_OPCODE_EXCEPTION : boolean := (C_ILL_OPCODE_EXCEPTION /= 0);
  constant IOPB_BUS_EXCEPTION   : boolean := (C_IOPB_BUS_EXCEPTION /= 0);
  constant DOPB_BUS_EXCEPTION   : boolean := (C_DOPB_BUS_EXCEPTION /= 0);
  constant IPLB_BUS_EXCEPTION   : boolean := (C_IPLB_BUS_EXCEPTION /= 0);
  constant DPLB_BUS_EXCEPTION   : boolean := (C_DPLB_BUS_EXCEPTION /= 0);
  constant DIV_ZERO_EXCEPTION   : boolean := (C_DIV_ZERO_EXCEPTION /= 0);
  constant FPU_EXCEPTION        : boolean := (C_FPU_EXCEPTION /= 0);
  constant FSL_EXCEPTION        : boolean := (C_FSL_EXCEPTION /= 0);
  constant USE_MUL_INSTR        : boolean := (C_USE_HW_MUL /= 0);
  constant USE_MUL64            : boolean := (C_USE_HW_MUL = 2);
  constant INTERRUPT_IS_EDGE    : boolean := (C_INTERRUPT_IS_EDGE /= 0);
  constant EDGE_IS_POSITIVE     : boolean := (C_EDGE_IS_POSITIVE /= 0);

  constant RESET_MSR : MSR_TYPE := C_RESET_MSR(MSR_REG_POS_TYPE);
  
  constant USE_EXCEPTIONS : boolean := (UNALIGNED_EXCEPTIONS or
                                        ILL_OPCODE_EXCEPTION or
                                        IOPB_BUS_EXCEPTION or
                                        DOPB_BUS_EXCEPTION or
                                        IPLB_BUS_EXCEPTION or
                                        DPLB_BUS_EXCEPTION or
                                        DIV_ZERO_EXCEPTION or
                                        (C_FSL_EXCEPTION /= 0) or
                                        FPU_EXCEPTION or
                                        C_USE_MMU > C_MMU_NONE);

  constant C_I_Ext_bool : boolean := USE_I_OPB or USE_I_PLB;

  -----------------------------------------------------------------------------
  -----------------------------------------------------------------------------
  -- Common component declarations
  -----------------------------------------------------------------------------
  -----------------------------------------------------------------------------
  component DPLB_Interface is