microblaze.vhd

Xilinx软核microblaze源码(VHDL)版本7.10

-------------------------------------------------------------------------------
-- $Id: microblaze.vhd,v 1.3 2008/01/16 15:46:49 stefana Exp $
-------------------------------------------------------------------------------
-- microblaze.vhd - Entity and architecture
--
--  ***************************************************************************
--  **  Copyright(C) 2003 by Xilinx, Inc. All rights reserved.               **
--  **                                                                       **
--  **  This text contains proprietary, confidential                         **
--  **  information of Xilinx, Inc. , is distributed by                      **
--  **  under license from Xilinx, Inc., and may be used,                    **
--  **  copied and/or disclosed only pursuant to the terms                   **
--  **  of a valid license agreement with Xilinx, Inc.                       **
--  **                                                                       **
--  **  Unmodified source code is guaranteed to place and route,             **
--  **  function and run at speed according to the datasheet                 **
--  **  specification. Source code is provided "as-is", with no              **
--  **  obligation on the part of Xilinx to provide support.                 **
--  **                                                                       **
--  **  Xilinx Hotline support of source code IP shall only include          **
--  **  standard level Xilinx Hotline support, and will only address         **
--  **  issues and questions related to the standard released Netlist        **
--  **  version of the core (and thus indirectly, the original core source). **
--  **                                                                       **
--  **  The Xilinx Support Hotline does not have access to source            **
--  **  code and therefore cannot answer specific questions related          **
--  **  to source HDL. The Xilinx Support Hotline will only be able          **
--  **  to confirm the problem in the Netlist version of the core.           **
--  **                                                                       **
--  **  This copyright and support notice must be retained as part           **
--  **  of this text at all times.                                           **
--  ***************************************************************************
--
-------------------------------------------------------------------------------
-- Filename:        microblaze.vhd
--
-- Description:     
--                  
-- VHDL-Standard:   VHDL'93/02
-------------------------------------------------------------------------------
-- Structure:   
--              microblaze.vhd
--
-------------------------------------------------------------------------------
-- Author:          goran
-- Revision:        $Revision: 1.3 $
-- Date:            $Date: 2008/01/16 15:46:49 $
--
-- History:
--   goran  2006-08-09    First Version
--
-------------------------------------------------------------------------------
-- Naming Conventions:
--      active low signals:                     "*_n"
--      clock signals:                          "clk", "clk_div#", "clk_#x" 
--      reset signals:                          "rst", "rst_n" 
--      generics:                               "C_*" 
--      user defined types:                     "*_TYPE" 
--      state machine next state:               "*_ns" 
--      state machine current state:            "*_cs" 
--      combinatorial signals:                  "*_com" 
--      pipelined or register delay signals:    "*_d#" 
--      counter signals:                        "*cnt*"
--      clock enable signals:                   "*_ce" 
--      internal version of output port         "*_i"
--      device pins:                            "*_pin" 
--      ports:                                  - Names begin with Uppercase 
--      processes:                              "*_PROCESS" 
--      component instantiations:               "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------

library IEEE;
use IEEE.std_logic_1164.all;

library Microblaze_v7_10_a;
use Microblaze_v7_10_a.MicroBlaze_ISA.all;
use Microblaze_v7_10_a.MicroBlaze_Types.all;

entity MicroBlaze is
  generic (

    -- Generic for source code optimization
    -- Currently used valuse:
    --       0 = Standard FPGA source based on target family
    --       1 = RTL code
    C_SCO : integer := 0;

    -- generics for "Data_Flow_I"
    C_FAMILY               : string                 := "virtex2";
    C_DATA_SIZE            : integer range 32 to 32 := 32;
    C_INSTANCE             : string                 := "microblaze";
    C_AREA_OPTIMIZED       : integer                := 0;
    C_INTERCONNECT         : integer                := 0;
    C_DPLB_DWIDTH          : integer                := 32;
    C_DPLB_NATIVE_DWIDTH   : integer                := 32;
    C_DPLB_BURST_EN        : integer                := 0;
    C_DPLB_P2P             : integer                := 0;
    C_IPLB_DWIDTH          : integer                := 32;
    C_IPLB_NATIVE_DWIDTH   : integer                := 32;
    C_IPLB_BURST_EN        : integer                := 0;
    C_IPLB_P2P             : integer                := 0;
    C_D_PLB                : integer                := 1;
    C_D_OPB                : integer                := 1;
    C_D_LMB                : integer                := 1;
    C_I_PLB                : integer                := 1;
    C_I_OPB                : integer                := 1;
    C_I_LMB                : integer                := 1;
    C_USE_MSR_INSTR        : integer                := 1;
    C_USE_PCMP_INSTR       : integer                := 1;
    C_USE_BARREL           : integer                := 1;
    C_USE_DIV              : integer                := 1;
    C_USE_HW_MUL           : integer                := 1;
    C_USE_FPU              : integer                := 0;
    C_UNALIGNED_EXCEPTIONS : integer                := 0;
    C_ILL_OPCODE_EXCEPTION : integer                := 0;
    C_IOPB_BUS_EXCEPTION   : integer                := 0;
    C_DOPB_BUS_EXCEPTION   : integer                := 0;
    C_IPLB_BUS_EXCEPTION   : integer                := 0;
    C_DPLB_BUS_EXCEPTION   : integer                := 0;
    C_DIV_ZERO_EXCEPTION   : integer                := 0;
    C_FPU_EXCEPTION        : integer                := 0;
    C_FSL_EXCEPTION        : integer                := 0;

    C_USE_MMU              : integer                := 0;
    C_MMU_DTLB_SIZE        : integer                := 8;
    C_MMU_ITLB_SIZE        : integer                := 4;
    C_MMU_TLB_ACCESS       : integer                := 3;
    C_MMU_ZONES            : integer                := 16;

    -- generics for PVR
    C_PVR       : integer                   := 0;  -- Which PVR mode None=0, Basic=1, Full=2
    C_PVR_USER1 : std_logic_vector(0 to 7)  := X"00";  -- User defined byte
    C_PVR_USER2 : std_logic_vector(0 to 31) := X"00000000";  -- User defined word

    -- generics for "Byte_HalfWord_Handle_I" 

    C_DYNAMIC_BUS_SIZING : integer := 1;  -- never used, should be removed

    -- reset value for MSR register
    C_RESET_MSR          : std_logic_vector(0 to 31) := (others => '0');
    C_OPCODE_0x0_ILLEGAL : integer                   := 0;

    -- generics for HW debugging
    C_DEBUG_ENABLED         : integer              := 1;
    C_NUMBER_OF_PC_BRK      : integer range 0 to 8 := 1;
    C_NUMBER_OF_RD_ADDR_BRK : integer range 0 to 4 := 1;
    C_NUMBER_OF_WR_ADDR_BRK : integer range 0 to 4 := 1;

    -- generics for interrupts
    C_INTERRUPT_IS_EDGE : integer := 0;
    C_EDGE_IS_POSITIVE  : integer := 1;

    -- generics for FSL Links
    C_FSL_LINKS               : integer range 0 to 16:= 1;
    C_FSL_DATA_SIZE           : integer := 32;    -- should be constrained to 32
    C_USE_EXTENDED_FSL_INSTR  : integer := 0;

    -- Generics for Instruction Cache
    C_ICACHE_BASEADDR    : std_logic_vector(0 to 31) := X"00000000";
    C_ICACHE_HIGHADDR    : std_logic_vector(0 to 31) := X"3FFFFFFF";
    C_USE_ICACHE         : integer                   := 1;
    C_ALLOW_ICACHE_WR    : integer                   := 1;
    C_ADDR_TAG_BITS      : integer                   := 7;  -- can be eliminarted
                                                            -- from i/f
    C_CACHE_BYTE_SIZE    : integer                   := 4096;
    C_ICACHE_USE_FSL     : integer                   := 1;  -- always 1
    C_ICACHE_LINE_LEN    : integer                   := 4;
    C_ICACHE_ALWAYS_USED : integer                   := 0;

    -- Generics for Data Cache
    C_DCACHE_BASEADDR    : std_logic_vector(0 to 31) := X"00000000";
    C_DCACHE_HIGHADDR    : std_logic_vector(0 to 31) := X"3FFFFFFF";
    C_USE_DCACHE         : integer                   := 1;
    C_ALLOW_DCACHE_WR    : integer                   := 1;
    C_DCACHE_ADDR_TAG    : integer                   := 7;  -- can be eliminarted
                                                            -- from i/f
    C_DCACHE_BYTE_SIZE   : integer                   := 4096;
    C_DCACHE_USE_FSL     : integer                   := 1;  -- always 1
    C_DCACHE_LINE_LEN    : integer                   := 4;
    C_DCACHE_ALWAYS_USED : integer                   := 0
    );

  port (

    -- global ports
    Clk   : in std_logic;
    Reset : in std_logic;
    Mb_Reset : in std_logic;

    -- system execution flow control
    Interrupt  : in std_logic;
    Ext_BRK    : in std_logic;
    Ext_NM_BRK : in std_logic;

    -- debug execution flow control
    Dbg_Stop  : in  std_logic;
    MB_Halted : out std_logic;

    -- Instruction Interface Local Bus
    Instr_Addr : out std_logic_vector(0 to C_DATA_SIZE-1);
    I_AddrTag  : out std_logic_vector(0 to 3);
    Instr      : in  std_logic_vector(0 to 31);
    IFetch     : out std_logic;
    I_AS       : out std_logic;
    IReady     : in  std_logic;
    IWait      : in  std_logic;

    -- Instruction Interface PLB signals
    IPLB_M_ABort      : out std_logic;
    IPLB_M_ABus       : out std_logic_vector(0 to 31);
    IPLB_M_UABus      : out std_logic_vector(0 to 31);
    IPLB_M_BE         : out std_logic_vector(0 to (C_IPLB_DWIDTH-1)/8);
    IPLB_M_busLock    : out std_logic;
    IPLB_M_lockErr    : out std_logic;
    IPLB_M_MSize      : out std_logic_vector(0 to 1);
    IPLB_M_priority   : out std_logic_vector(0 to 1);
    IPLB_M_rdBurst    : out std_logic;
    IPLB_M_request    : out std_logic;
    IPLB_M_RNW        : out std_logic;
    IPLB_M_size       : out std_logic_vector(0 to 3);
    IPLB_M_TAttribute : out std_logic_vector(0 to 15);
    IPLB_M_type       : out std_logic_vector(0 to 2);
    IPLB_M_wrBurst    : out std_logic;
    IPLB_M_wrDBus     : out std_logic_vector(0 to C_IPLB_DWIDTH-1);
    IPLB_MBusy        : in  std_logic;
    IPLB_MRdErr       : in  std_logic;
    IPLB_MWrErr       : in  std_logic;
    IPLB_MIRQ         : in  std_logic;
    IPLB_MWrBTerm     : in  std_logic;
    IPLB_MWrDAck      : in  std_logic;
    IPLB_MAddrAck     : in  std_logic;
    IPLB_MRdBTerm     : in  std_logic;
    IPLB_MRdDAck      : in  std_logic;
    IPLB_MRdDBus      : in  std_logic_vector(0 to C_IPLB_DWIDTH-1);
    IPLB_MRdWdAddr    : in  std_logic_vector(0 to 3);
    IPLB_MRearbitrate : in  std_logic;
    IPLB_MSSize       : in  std_logic_vector(0 to 1);
    IPLB_MTimeout     : in  std_logic;

    -- Instruction Interface OPB Bus
    IM_ABus      : out std_logic_vector(0 to C_DATA_SIZE-1);
    IM_BE        : out std_logic_vector(0 to (C_DATA_SIZE-1)/8);
    IM_busLock   : out std_logic;
    IM_DBus      : out std_logic_vector(0 to C_DATA_SIZE-1);
    IM_request   : out std_logic;
    IM_RNW       : out std_logic;
    IM_select    : out std_logic;
    IM_seqAddr   : out std_logic;
    IOPB_DBus    : in  std_logic_vector(0 to 31);
    IOPB_errAck  : in  std_logic;
    IOPB_MGrant  : in  std_logic;
    IOPB_retry   : in  std_logic;
    IOPB_timeout : in  std_logic;
    IOPB_xferAck : in  std_logic;

    -- Data Interface Local Bus
    Data_Addr    : out std_logic_vector(0 to C_DATA_SIZE-1);
    D_AddrTag    : out std_logic_vector(0 to 3);
    Data_Read    : in  std_logic_vector(0 to C_DATA_SIZE-1);
    Data_Write   : out std_logic_vector(0 to C_DATA_SIZE-1);
    D_AS         : out std_logic;
    Read_Strobe  : out std_logic;
    Write_Strobe : out std_logic;
    DReady       : in  std_logic;
    DWait        : in  std_logic;
    Byte_Enable  : out std_logic_vector(0 to (C_DATA_SIZE-1)/8);

    -- Data Interface PLB signals
    DPLB_M_ABort      : out std_logic;
    DPLB_M_ABus       : out std_logic_vector(0 to 31);
    DPLB_M_UABus      : out std_logic_vector(0 to 31);
    DPLB_M_BE         : out std_logic_vector(0 to (C_DPLB_DWIDTH-1)/8);
    DPLB_M_busLock    : out std_logic;
    DPLB_M_lockErr    : out std_logic;
    DPLB_M_MSize      : out std_logic_vector(0 to 1);
    DPLB_M_priority   : out std_logic_vector(0 to 1);
    DPLB_M_rdBurst    : out std_logic;
    DPLB_M_request    : out std_logic;
    DPLB_M_RNW        : out std_logic;
    DPLB_M_size       : out std_logic_vector(0 to 3);
    DPLB_M_TAttribute : out std_logic_vector(0 to 15);
    DPLB_M_type       : out std_logic_vector(0 to 2);
    DPLB_M_wrBurst    : out std_logic;
    DPLB_M_wrDBus     : out std_logic_vector(0 to C_DPLB_DWIDTH-1);
    DPLB_MBusy        : in  std_logic;
    DPLB_MRdErr       : in  std_logic;
    DPLB_MWrErr       : in  std_logic;
    DPLB_MIRQ         : in  std_logic;
    DPLB_MWrBTerm     : in  std_logic;
    DPLB_MWrDAck      : in  std_logic;
    DPLB_MAddrAck     : in  std_logic;
    DPLB_MRdBTerm     : in  std_logic;
    DPLB_MRdDAck      : in  std_logic;
    DPLB_MRdDBus      : in  std_logic_vector(0 to C_DPLB_DWIDTH-1);
    DPLB_MRdWdAddr    : in  std_logic_vector(0 to 3);
    DPLB_MRearbitrate : in  std_logic;
    DPLB_MSSize       : in  std_logic_vector(0 to 1);
    DPLB_MTimeout     : in  std_logic;

    -- Data Interface OPB Bus
    DM_ABus      : out std_logic_vector(0 to C_DATA_SIZE-1);
    DM_BE        : out std_logic_vector(0 to (C_DATA_SIZE-1)/8);
    DM_busLock   : out std_logic;
    DM_DBus      : out std_logic_vector(0 to C_DATA_SIZE-1);
    DM_request   : out std_logic;
    DM_RNW       : out std_logic;
    DM_select    : out std_logic;
    DM_seqAddr   : out std_logic;
    DOPB_DBus    : in  std_logic_vector(0 to C_DATA_SIZE-1);
    DOPB_errAck  : in  std_logic;
    DOPB_MGrant  : in  std_logic;
    DOPB_retry   : in  std_logic;
    DOPB_timeout : in  std_logic;
    DOPB_xferAck : in  std_logic;

    -- Debug Signals
    Dbg_Clk     : in  std_logic;
    Dbg_TDI     : in  std_logic;
    Dbg_TDO     : out std_logic;
    Dbg_Reg_En  : in  std_logic_vector(0 to 4);
    Dbg_Shift   : in  std_logic;
    Dbg_Capture : in  std_logic;        -- Read
    Dbg_Update  : in  std_logic;        -- Write
    Debug_Rst   : in  std_logic;

    -- Trace signals