shift_logic_gti.vhd

Xilinx软核microblaze源码(VHDL)版本7.10

--SINGLE_FILE_TAG
-------------------------------------------------------------------------------
-- $Id: shift_logic_gti.vhd,v 1.1 2007/10/12 09:11:36 stefana Exp $
-------------------------------------------------------------------------------
-- Shift_Logic - entity/architecture
-------------------------------------------------------------------------------
--
-- ****************************************************************************
-- ** Copyright(C) 2001-2005 by Xilinx, Inc. All rights reserved.
-- **
-- ** This text contains proprietary, confidential information of
-- ** Xilinx, Inc. , is distributed by under license from Xilinx, Inc.,
-- ** and may be used, copied and/or disclosed only pursuant to the
-- ** terms of a valid license agreement with Xilinx, Inc. 
-- **
-- ** Unmodified source code is guaranteed to place and route, 
-- ** function and run at speed according to the datasheet
-- ** specification. Source code is provided "as-is", with no
-- ** obligation on the part of Xilinx to provide support.
-- **
-- ** Xilinx Hotline support of source code IP shall only include
-- ** standard level Xilinx Hotline support, and will only address
-- ** issues and questions related to the standard released Netlist
-- ** version of the core (and thus indirectly, the original core source
-- **
-- ** The Xilinx Support Hotline does not have access to source
-- ** code and therefore cannot answer specific questions related
-- ** to source HDL. The Xilinx Support Hotline will only be able
-- ** to confirm the problem in the Netlist version of the core.
-- **
-- ** This copyright and support notice must be retained as part
-- ** of this text at all times.
-- ****************************************************************************
--
-------------------------------------------------------------------------------
-- Filename:        shift_logic.vhd
-- Version:         v1.00a
-- Description:     Implement the functions needed for shift right and the
--                  logical instructions
--                  
-------------------------------------------------------------------------------
-- Structure:   
--              shift_logic.vhd
--
-------------------------------------------------------------------------------
-- Author:          goran
-- History:
--   goran  2001-03-05    First Version of entity
--   goran  2001-03-09    First Version of architecture
--   ltg    2005-04-20    Modified for GTi
--
-------------------------------------------------------------------------------
-- Naming Conventions:
--      active low signals:                     "*_n"
--      clock signals:                          "clk", "*_clk"
--      reset signals:                          "rst", "*_rst", "reset"
--      generics:                               All uppercase, starting with: "C_"
--      constants:                              All uppercase, not starting with: "C_"
--      state machine next state:               "*_next_state"
--      state machine current state:            "*_curr_state"
--      pipelined signals:                      "*_d#"
--      counter signals:                        "*_cnt_*" , "*_counter_*", "*_count_*"
--      internal version of output port:        "*_i"
--      ports:                                  Names begin with uppercase
--      component instantiations:               "<ENTITY_>I_<#|FUNC>" , "ENTITY>_I#" 
--
-- Signals starting with IF, OF, EX, MEM, or WB indicate that they start in that
-- stage:
--
--    IF                                -- instruction fetch
--    OF                                -- operand fetch
--    EX                                -- execute
--    MEM                               -- memory
--    WB                                -- write back
-------------------------------------------------------------------------------

library IEEE;
use IEEE.std_logic_1164.all;

library Microblaze_v7_10_a;
use Microblaze_v7_10_a.MicroBlaze_ISA.all;
use Microblaze_v7_10_a.MicroBlaze_Types.all;

library unisim;
use unisim.vcomponents.all;

-------------------------------------------------------------------------------
-- Port declarations
-------------------------------------------------------------------------------

entity Shift_Logic_Module_gti is
  generic (
    C_USE_PCMP_INSTR : boolean               := true;
    C_TARGET         : TARGET_FAMILY_TYPE    := virtex4
    -- pragma xilinx_rtl_off
;
    C_U_SET          : string                := "shiftlogic"
    -- pragma xilinx_rtl_on
    );
  port (
    EX_Op1                : in  DATA_TYPE;
    EX_Op2                : in  DATA_TYPE;
    EX_CarryIn            : in  std_logic;
    EX_Sext_Op            : in  SEXT_OP_TYPE;
    EX_Shift_Op           : in  SHIFT_OP_TYPE;
    EX_Logic_Op           : in  LOGIC_OP_TYPE;
    EX_Sign_Extend_Sel    : in  boolean;
    EX_Pattern_Cmp_Sel    : in  boolean;
    EX_Logic_Sel          : in  boolean;
    EX_Shift_Logic_Result : out DATA_TYPE;
    EX_Shift_Carry        : out std_logic
    );

end entity Shift_Logic_Module_gti;

-------------------------------------------------------------------------------
-- Architecture section
-------------------------------------------------------------------------------

architecture IMP of Shift_Logic_Module_gti is

  signal shift_result : DATA_TYPE;
  signal shifted_msb  : std_logic;      -- right shift sign bit
  signal sext_result  : DATA_TYPE;
  signal sext         : DATA_TYPE;      -- Sign extension
  signal logic_result : DATA_TYPE;
  signal pcmp_result  : DATA_TYPE;
  
  signal sext_shift_result              : DATA_TYPE;
  signal sext_shift_logic_result        : DATA_TYPE;
  signal sext_shift_logic_result_masked : DATA_TYPE;
  signal sign_0_15                      : std_logic;
  signal sign_16_23                     : std_logic;
  signal mask_0_15                      : std_logic;
  signal mask_16_23                     : std_logic;

  signal msb_byte_eq   : boolean;
  signal lsb_2_byte_eq : boolean;
  signal lsb_1_byte_eq : boolean;
  signal lsb_byte_eq   : boolean;

  attribute keep  : string;
  attribute U_SET : string;
  attribute INIT  : string;
  attribute RLOC  : string;

  attribute keep of sign_0_15  : signal is "true";
  attribute keep of sign_16_23 : signal is "true";
  attribute keep of mask_0_15  : signal is "true";
  attribute keep of mask_16_23 : signal is "true";
-------------------------------------------------------------------------------
-- Begin architecture
-------------------------------------------------------------------------------
  
begin

  -----------------------------------------------------------------------------
  -- Handle all types of right shift operations
  -----------------------------------------------------------------------------
  Shift_Operation : process (EX_CarryIn, EX_Op1, EX_Shift_Op) is
  begin  -- process Shift_Operation
    -- Calculate the new MSb for specific shift operation
    case EX_Shift_Op is
      when SRA_DEC => shifted_msb <= EX_Op1(EX_Op1'left);
      when SRC_DEC => shifted_msb <= EX_CarryIn;
      when others  => shifted_msb <= '0';  -- SRL, SEXT
    end case;
  end process Shift_Operation;

  -- Do the right shift
  shift_result <= shifted_msb & EX_Op1(0 to DATA_TYPE'length-2);

  -----------------------------------------------------------------------------
  -- Handle 8 and 16 bit sign extension operations
  -----------------------------------------------------------------------------
  Sign_Extend_Handler : process (EX_Op1, EX_Sext_Op) is
    variable sign_bit : std_logic;
  begin  -- process Sign_Extend_Handler
    -- Generate the Sign Extended bus: sext
    if EX_Sext_Op = SEXT_OP_8 then
      sign_bit   := EX_Op1(BYTE_SIGN_POS);
      sign_0_15  <= sign_bit;
      sign_16_23 <= sign_bit;
      mask_0_15  <= sign_bit;
      mask_16_23 <= sign_bit;
    elsif EX_Sext_Op = SEXT_OP_16 then
      sign_bit   := EX_Op1(DOUBLET_SIGN_POS);
      sign_0_15  <= sign_bit;
      sign_16_23 <= '0';
      mask_0_15  <= sign_bit;
      mask_16_23 <= '1';
    else
      sign_0_15  <= '0';
      sign_16_23 <= '0';
      mask_0_15  <= '1';
      mask_16_23 <= '1';
    end if;
  end process Sign_Extend_Handler;

  sext_result(0 to 15)  <= (others => '1') when sign_0_15 = '1'  else EX_Op1(0 to 15);
  sext_result(16 to 23) <= (others => '1') when sign_16_23 = '1' else EX_Op1(16 to 23);
  sext_result(24 to 31) <= EX_Op1(24 to 31);

  sext_shift_result <= sext_result when EX_Sign_Extend_Sel else shift_result;

  -----------------------------------------------------------------------------
  -- Handle all logic operations
  -----------------------------------------------------------------------------
  Logic_Handler : process (EX_Logic_Op, EX_Op1, EX_Op2) is
  begin  -- process Logic_Handler
    case EX_Logic_Op is
      when LOGIC_OR_DEC    => logic_result <= EX_Op1 or EX_Op2;
      when LOGIC_AND_DEC   => logic_result <= EX_Op1 and EX_Op2;
      when LOGIC_XOR_DEC   => logic_result <= EX_Op1 xor EX_Op2;
      when LOGIC_ANDN_DEC  => logic_result <= EX_Op1 and not EX_Op2;
      when others => null;
    end case;
  end process Logic_Handler;

  Using_RTL: if (C_TARGET = RTL) generate
    sext_shift_logic_result <= logic_result when EX_Logic_Sel else sext_shift_result;    
  end generate Using_RTL;

  Using_FPGA : if (C_TARGET /= RTL) generate
    signal EX_Logic_Sel_std : std_logic;
  begin
    EX_Logic_Sel_std <= '1' when EX_Logic_Sel else '0';
    All_Bits : for I in DATA_TYPE'range generate
      MUXF5_I1 : MUXF5
        port map (
          O  => sext_shift_logic_result(I),  -- [out std_logic]
          I0 => sext_shift_result(I),        -- [in  std_logic]
          I1 => logic_result(I),             -- [in  std_logic]
          S  => EX_Logic_Sel_std);           -- [in std_logic]      
    end generate All_Bits;
  end generate Using_FPGA;

  sext_shift_logic_result_masked(0 to 15)  <= (others => '0') when mask_0_15 = '0'  else sext_shift_logic_result(0 to 15);
  sext_shift_logic_result_masked(16 to 23) <= (others => '0') when mask_16_23 = '0' else sext_shift_logic_result(16 to 23);
  sext_shift_logic_result_masked(24 to 31) <= sext_shift_logic_result(24 to 31);
  
  -----------------------------------------------------------------------------
  -- conditional pattern compare handling
  -----------------------------------------------------------------------------
  No_PCMP_instr : if (not C_USE_PCMP_INSTR) generate
    -- Result selection
    EX_Shift_Logic_Result <= sext_shift_logic_result_masked;
  end generate No_PCMP_instr;

  Use_PCMP_instr : if (C_USE_PCMP_INSTR) generate
    EX_Shift_Logic_Result <= pcmp_result when EX_Pattern_Cmp_Sel else sext_shift_logic_result_masked;
    
--    -- Result selection
--    EX_Shift_Logic_Result <= pcmp_result when EX_Pattern_Cmp_Sel else
--                             logic_result when EX_Logic_Sel else
--                             sext_result when EX_Sign_Extend_Sel else
--                             shift_result;

    -----------------------------------------------------------------------------
    -- Handle pattern compare operations (uses same opcode as logic operations)
    -----------------------------------------------------------------------------

    msb_byte_eq   <= EX_Op1(BYTE_MSB_POS_TYPE) = EX_Op2(BYTE_MSB_POS_TYPE);
    lsb_2_byte_eq <= EX_Op1(BYTE_LSB_2_POS_TYPE) = EX_Op2(BYTE_LSB_2_POS_TYPE);
    lsb_1_byte_eq <= EX_Op1(BYTE_LSB_1_POS_TYPE) = EX_Op2(BYTE_LSB_1_POS_TYPE);
    lsb_byte_eq   <= EX_Op1(BYTE_LSB_POS_TYPE) = EX_Op2(BYTE_LSB_POS_TYPE);
    
    Pattern_Compare_Handler: process (EX_Logic_Op, lsb_1_byte_eq,
                                      lsb_2_byte_eq, lsb_byte_eq, msb_byte_eq) is
    begin  -- process Logic_Handler
      
      case EX_Logic_Op is
        when PCMPBF_DEC =>
          if msb_byte_eq then
            pcmp_result(PCMP_RES_POS_TYPE) <= PCMPBF_B0_MATCH;
          elsif lsb_2_byte_eq then
            pcmp_result(PCMP_RES_POS_TYPE) <= PCMPBF_B1_MATCH;
          elsif lsb_1_byte_eq then
            pcmp_result(PCMP_RES_POS_TYPE) <= PCMPBF_B2_MATCH;
          elsif lsb_byte_eq then
            pcmp_result(PCMP_RES_POS_TYPE) <= PCMPBF_B3_MATCH;
          else
            pcmp_result(PCMP_RES_POS_TYPE) <= PCMPBF_NO_MATCH;
          end if;
        when PCMPEQ_DEC =>
          if msb_byte_eq and lsb_2_byte_eq and lsb_1_byte_eq and lsb_byte_eq then
            pcmp_result(PCMP_RES_POS_TYPE) <= PCMPEQ_MATCH;
          else
            pcmp_result(PCMP_RES_POS_TYPE) <= PCMPEQ_NO_MATCH;
          end if;
        when PCMPNE_DEC =>
          if msb_byte_eq and lsb_2_byte_eq and lsb_1_byte_eq and lsb_byte_eq then
            pcmp_result(PCMP_RES_POS_TYPE) <= PCMPNE_NO_MATCH;
          else
            pcmp_result(PCMP_RES_POS_TYPE) <= PCMPNE_MATCH;
          end if;
        when others => pcmp_result <= (others => '0');
      end case;
    end process Pattern_Compare_Handler;
    
  end generate Use_PCMP_instr;

  -----------------------------------------------------------------------------
  -- Carry out is always the LSB of Op1
  -----------------------------------------------------------------------------
  EX_Shift_Carry <= EX_Op1(EX_Op1'right);
  
end architecture IMP;