byte_doublet_handle.vhd

Xilinx软核microblaze源码(VHDL)版本7.10

        -- 0   1     1     0         X       X     D(8:15)   |     0   1 
        -- 1   0     1     0         X       X     D(16:23)  |     1   0 
        -- 1   1     1     0         X       X     D(24:31)  |     1   1 
        -------------------------------------------------------------------------
        READ_SEL_LEFT_I : LUT3
          generic map(INIT => X"AB")
          port map (
            O  => sel_LSB(sel_LSB'left),     --[out]
            I0 => Low_Addr(Low_Addr'left),   --[in]
            I1 => iByte,                     --[in]
            I2 => iDoublet                   --[in]
            );
        READ_SEL_RIGHT_I : LUT2
          generic map(INIT => X"B")
          port map (
            O  => sel_LSB(sel_LSB'right),    --[out]
            I0 => Low_Addr(Low_Addr'right),  --[in]
            I1 => iByte                      --[in]
            );    

        -- Data_Read_To_Mux <= Data_Read(0 to 7) &
        --                     Data_Read(8 to 15) &
        --                     Data_Read(16 to 23) &
        --                     Data_Read(24 to 31);

-------------------------------------------------------------------------
-- Read Data Steering mux. Generates both least significant byte and
-- least significant word.
-- Implements the following process on the LSB:
--
--  Extend_Data_Read_Mux_LSB : process (sel_LSB, Data_Read) is
--  begin  -- process Extend_Data_Read_Mux_LSB      -- case sel_LSB is
--    when "11" =>
--      extend_Data_Read_I(24 to 31) <= Data_Read(24 to 31);
--    when "10" =>
--      extend_Data_Read_I(24 to 31) <= Data_Read(16 to 23);
--    when "01" =>
--      extend_Data_Read_I(24 to 31) <= Data_Read(8 to 15);
--    when "00" =>
--      extend_Data_Read_I(24 to 31) <= Data_Read(0 to 7);
--    when others => null;
--   end case;
--  end process Extend_Data_Read_Mux_LSB;
-------------------------------------------------------------------------
        Data_Read_Steering_I : Data_Read_Steering
          generic map (
            C_TARGET => C_TARGET)            -- [TARGET_FAMILY_TYPE]
          port map (
            D_In    => Data_Read,            -- [in  std_logic_vector(0 to 31)]
            Sel_LSB => Sel_LSB,              -- [in  std_logic_vector(0 to 1)]
            D_Out   => extend_Data_Read_I);  -- [out std_logic_vector(0 to 31)]

--     EXT_DATA_READ_MUX_LSB_I: mux_encode_sel
--       generic map (
--         C_TARGET => C_TARGET, 
--         C_Y      => 0,
--         C_X      => 2*Get_Reg_File_Area(C_TARGET),
--         C_U_SET  => C_U_SET, 
--         C_DW     => 8,
--         C_NB     => 4,
--         C_BE     => True)
--       port map (
--         D        => Data_Read_To_Mux,
--         S        => sel_LSB,                                --[in]
--         Y        => extend_Data_Read_I(24 to 31),  --[out]
--         YL       => extend_Data_Read_I(16 to 23) --[out]
--         );

--     -- In Read the upper doublet is not affected by data steering since they are
--     -- only used for word accesses
--     extend_Data_Read_I(DOUBLET_MSB_POS_TYPE) <= Data_Read(DOUBLET_MSB_POS_TYPE);

        -- Write Data Steering Logic function: MSB and LSB_2
        --------------------------------------------------------------------------- 
        --  addr        type       desired bus connection             | mux selects 
        -- A0  A1   Byte Doublet  D(0:7)   D(8:15)  D(16:23) D(24:31) |   S0  S1 
        --------------------------------------------------------------------------- 
        -- X   X     0     0      D(0:7)   D(8:15)  D(16:23) D(24:31) |     0   0 
        -- 0   X     0     1      D(16:23) D(24:31) D(16:23) D(24:31) |     1   0 
        -- 1   X     0     1      D(16:23) D(24:31) D(16:23) D(24:31) |     1   0 
        -- 0   0     1     0      D(24:31) D(24:31) D(24:31) D(24:31) |     1   1 
        -- 0   1     1     0      D(24:31) D(24:31) D(24:31) D(24:31) |     1   1 
        -- 1   0     1     0      D(24:31) D(24:31) D(24:31) D(24:31) |     1   1 
        -- 1   1     1     0      D(24:31) D(24:31) D(24:31) D(24:31) |     1   1 
        ---------------------------------------------------------------------------
        -- S0 <= Byte or Doublet;
        -- S1 <= Byte;

        sel_Write_Mux_MSB(sel_Write_Mux_MSB'right) <= not iByte;

        WRITE_MSB_SEL_LEFT_I : LUT2     -- iDoublet or iByte
          generic map(INIT => X"E")
          port map (
            O  => sel_Write_Mux_MSB(sel_Write_Mux_MSB'left),  --[out]
            I0 => iDoublet,             --[in]
            I1 => iByte                 --[in]
            );         

        Data_Write_To_Mux_MSB <= Data_Write(8 to 15) &
                                 Data_Write(0 to 7) &
                                 Data_Write(24 to 31) &
                                 Data_Write(16 to 23);

        EXT_DATA_WRITE_MUX_MSB_I : mux4_8
          generic map (
            C_TARGET => C_TARGET,       -- [TARGET_FAMILY_TYPE]
            C_BE     => true)           -- [boolean]
          port map (
            D  => Data_Write_To_Mux_MSB,  -- [in  std_logic_vector(0 to 31)]
            S  => sel_Write_Mux_MSB,    -- [in  std_logic_vector(0 to 1)]
            Y  => extend_Data_Write_I(0 to 7),  -- [out std_logic_vector(0 to 7)]
            YL => extend_Data_Write_I(8 to 15));  -- [out std_logic_vector(0 to 7)]

        -- Write Data Steering Logic function: LSB_1
        --------------------------------------------------------------------------- 
        --  addr        type       desired bus connection             | mux selects 
        -- A0  A1   Byte Doublet  D(0:7)   D(8:15)  D(16:23) D(24:31) |   S0   
        --------------------------------------------------------------------------- 
        -- X   X     0     0      D(0:7)   D(8:15)  D(16:23) D(24:31) |     0    
        -- 0   X     0     1      D(16:23) D(24:31) D(16:23) D(24:31) |     0    
        -- 1   X     0     1      D(16:23) D(24:31) D(16:23) D(24:31) |     0   
        -- 0   0     1     0      D(24:31) D(24:31) D(24:31) D(24:31) |     1    
        -- 0   1     1     0      D(24:31) D(24:31) D(24:31) D(24:31) |     1    
        -- 1   0     1     0      D(24:31) D(24:31) D(24:31) D(24:31) |     1    
        -- 1   1     1     0      D(24:31) D(24:31) D(24:31) D(24:31) |     1    
        ---------------------------------------------------------------------------    

        extend_Data_Write_I(16 to 23) <= Data_Write(16 to 23) when iByte = '0'
                                         else Data_Write(24 to 31);

        extend_Data_Write_I(24 to 31) <= Data_Write(24 to 31);

      end generate Use_Dynamic_Bus_Sizing;

      Extend_Data_Read  <= extend_Data_Read_I;
      Extend_Data_Write <= extend_Data_Write_I;

      ---------------------------------------------------------------------------    
      -- Hangle lower two address bits
      ---------------------------------------------------------------------------    

      -- Low_Addr_Handle : process (Low_Addr, Byte, Doublet) is
      -- begin  -- process Low_Addr_Handle
      --   if Byte then
      --     Low_Addr_Out <= Low_Addr;
      --   elsif Doublet then
      --     Low_Addr_Out(Low_Addr'right) <= '0';
      --     Low_Addr_Out(Low_Addr'left)  <= Low_Addr(Low_Addr'left);
      --   else
      --     Low_Addr_Out <= "00";
      --   end if;
      -- end process Low_Addr_Handle;

      LOW_ADDR_OUT_LEFT_I : LUT3
        generic map(INIT => X"A8")
        port map (
          O  => Low_Addr_Out(Low_Addr'left),   --[out]
          I0 => Low_Addr(Low_Addr'left),       --[in]
          I1 => iDoublet,                      --[in]
          I2 => iByte                          --[in]
          );
      LOW_ADDR_OUT_RIGHT_I : LUT2
        generic map(INIT => X"8")
        port map (
          O  => Low_Addr_Out(Low_Addr'right),  --[out]
          I0 => iByte,                         --[in]
          I1 => Low_Addr(Low_Addr'right)       --[in]
          );
    end generate Data_Size_Is_32;

  end generate Using_FPGA;

  -----------------------------------------------------------------------------
  -----------------------------------------------------------------------------
  -----------------------------------------------------------------------------
  -- RTL version
  -----------------------------------------------------------------------------
  -----------------------------------------------------------------------------
  -----------------------------------------------------------------------------

  Using_RTL : if (C_TARGET = RTL) generate
  
    ---------------------------------------------------------------------------
    -- Low Addr Out
    ---------------------------------------------------------------------------
    Low_Addr_Handle : process (Low_Addr, Byte, Doublet) is
    begin  -- process Low_Addr_Handle
      if Byte then
        Low_Addr_Out <= Low_Addr;
      elsif Doublet then
        Low_Addr_Out(Low_Addr'right) <= '0';
        Low_Addr_Out(Low_Addr'left)  <= Low_Addr(Low_Addr'left);
      else
        Low_Addr_Out <= "00";
      end if;
    end process Low_Addr_Handle;

    ---------------------------------------------------------------------------
    -- Byte Enable
    ---------------------------------------------------------------------------
    Byte_Enable_Handler : process (Byte, Doublet, Low_Addr) is
    begin  -- process Byte_Enable_Handler                                         
      byte_Enable_I <= (others => '0');
      if Byte then
        case Low_Addr is
          when "00"   => byte_Enable_I(0) <= '1';
          when "01"   => byte_Enable_I(1) <= '1';
          when "10"   => byte_Enable_I(2) <= '1';
          when "11"   => byte_Enable_I(3) <= '1';
          when others => null;
        end case;
      elsif Doublet then
        case Low_Addr(Low_Addr'left) is
          when '0'    => byte_Enable_I(0 to 1) <= "11";
          when '1'    => byte_Enable_I(2 to 3) <= "11";
          when others => null;
        end case;
      else
        byte_Enable_I <= (others => '1');
      end if;
    end process Byte_Enable_Handler;

    Byte_Enable <= byte_Enable_I;

    ---------------------------------------------------------------------------
    -- Data Reading steering
    ---------------------------------------------------------------------------
    Steering : process(Byte, Doublet, Low_Addr, Data_Read) is
      variable Sel_LSB : std_logic_vector(0 to 1);
    begin  -- process Steering
      if Byte then
        sel_LSB := Low_Addr;
      elsif Doublet then
        sel_LSB := Low_Addr(Low_Addr'left) & '1';
      else
        sel_LSB := "11";
      end if;
      Extend_Data_Read(0 to 15) <= Data_Read(0 to 15);
      if (Sel_LSB(0) = '0') then
        Extend_Data_Read(16 to 23) <= Data_Read(0 to 7);
      else
        Extend_Data_Read(16 to 23) <= Data_Read(16 to 23);
      end if;
      case Sel_LSB is
        when "00"   => Extend_Data_Read(24 to 31) <= Data_Read(0 to 7);
        when "01"   => Extend_Data_Read(24 to 31) <= Data_Read(8 to 15);
        when "10"   => Extend_Data_Read(24 to 31) <= Data_Read(16 to 23);
        when "11"   => Extend_Data_Read(24 to 31) <= Data_Read(24 to 31);
        when others => null;
      end case;
    end process Steering;

    ---------------------------------------------------------------------------
    -- Data Write mirroring
    ---------------------------------------------------------------------------
    Mirroring : process (Byte, Doublet, Data_Write) is
    begin  -- process Mirroring
      if (Byte) then
        extend_Data_Write_I(0 to 7)   <= Data_Write(24 to 31);
        extend_Data_Write_I(8 to 15)  <= Data_Write(24 to 31);
        extend_Data_Write_I(16 to 23) <= Data_Write(24 to 31);
        extend_Data_Write_I(24 to 31) <= Data_Write(24 to 31);
      elsif (Doublet) then
        extend_Data_Write_I(0 to 15)  <= Data_Write(16 to 31);
        extend_Data_Write_I(16 to 31) <= Data_Write(16 to 31);
      else
        extend_Data_Write_I <= Data_Write;
      end if;
    end process Mirroring;

    Extend_Data_Write <= extend_Data_Write_I;

  end generate Using_RTL;

end architecture IMP;