byte_doublet_handle.vhd

Xilinx软核microblaze源码(VHDL)版本7.10

--SINGLE_FILE_TAG
-------------------------------------------------------------------------------
-- $Id: byte_doublet_handle.vhd,v 1.1 2007/10/12 09:11:36 stefana Exp $
-------------------------------------------------------------------------------
-- Byte_Doublet_Handle - entity/architecture
-------------------------------------------------------------------------------
--
--                  ****************************
--                  ** Copyright Xilinx, Inc. **
--                  ** All rights reserved.   **
--                  ****************************
--
-------------------------------------------------------------------------------
-- Filename:        byte_doublet_handle.vhd
-- Version:         v1.00a
-- Description:     Handles write data mirroring and read data steering
--                  
-------------------------------------------------------------------------------
-- Structure:   
--              byte_doublet_handle.vhd
--
-------------------------------------------------------------------------------
-- Author:          goran
-- History:
--   goran  2001-03-05    First Version
--   BLT    2001-04-16    Modified M_DBus FF's to be synch reset
--   BLT    2001-04-23    Forced Read_LSB mux to use F5MUX
--   goran  2002-05-10    Remove all ISA usage and mux_encode_sel
-- ^^^^^^
--      1. Modified sel_LSB_1 in Extend_Data_Read_Sel_LSB_1 to use
--         Low_Addr'left instead of Low_Addr'right
--      2. Modified sel_LSB in Extend_Data_Read_Sel_LSB to use
--         Low_Addr(Low_Addr'left) instead of Low_Addr(1)
--      3. Use mux_encode_sel for Extend_Data_Read_Mux_LSB
--      4. Remove all usage of mux_encode_sel and added fixed size muxes
--         Needed to pass XST
-- ~~~~~~
--
-------------------------------------------------------------------------------
-- Naming Conventions:
--      active low signals:                     "*_n"
--      clock signals:                          "clk", "clk_div#", "clk_#x" 
--      reset signals:                          "rst", "rst_n" 
--      generics:                               "C_*" 
--      user defined types:                     "*_TYPE" 
--      state machine next state:               "*_ns" 
--      state machine current state:            "*_cs" 
--      combinatorial signals:                  "*_com" 
--      pipelined or register delay signals:    "*_d#" 
--      counter signals:                        "*cnt*"
--      clock enable signals:                   "*_ce" 
--      internal version of output port         "*_i"
--      device pins:                            "*_pin" 
--      ports:                                  - Names begin with Uppercase 
--      processes:                              "*_PROCESS" 
--      component instantiations:               "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------

library IEEE;
use IEEE.std_logic_1164.all;

library Microblaze_v7_10_a;
use Microblaze_v7_10_a.MicroBlaze_Types.all;
use Microblaze_v7_10_a.all;
-------------------------------------------------------------------------------
-- Port declarations
-------------------------------------------------------------------------------

entity Byte_Doublet_Handle is

  generic (
    C_TARGET             : TARGET_FAMILY_TYPE;
    C_OPB_WIDTH          : natural range 4 to 64 := 32;
    C_DATA_SIZE          : natural range 4 to 64 := 32
    );
  port (
    Clk               : in  std_logic;
    -- Reset             : in  boolean;
    Byte              : in  boolean;
    Doublet           : in  boolean;
    Op1_Low           : in  std_logic_vector(0 to 1);
    Op2_Low           : in  std_logic_vector(0 to 1);
    Data_Read         : in  std_logic_vector(0 to C_OPB_WIDTH-1);
    Data_Write        : in  std_logic_vector(0 to C_DATA_SIZE-1);
    Extend_Data_Write : out std_logic_vector(0 to C_OPB_WIDTH-1);
    Extend_Data_Read  : out std_logic_vector(0 to C_DATA_SIZE-1);
    Byte_Enable       : out std_logic_vector(0 to (C_OPB_WIDTH-1)/8);
    Low_Addr_Out      : out std_logic_vector(0 to 1)
    );

end entity Byte_Doublet_Handle;

-------------------------------------------------------------------------------
-- Architecture section
-------------------------------------------------------------------------------

library Unisim;
use Unisim.vcomponents.all;

architecture IMP of Byte_Doublet_Handle is
  
  constant C_DYNAMIC_BUS_SIZING : boolean := true;

  component mux4_8 is
    generic (
      C_TARGET : TARGET_FAMILY_TYPE;
      C_BE     : boolean);
    port (
      D  : in  std_logic_vector(0 to 31);
      S  : in  std_logic_vector(0 to 1);
      Y  : out std_logic_vector(0 to 7);
      YL : out std_logic_vector(0 to 7));
  end component mux4_8;

  component Data_Read_Steering is
    generic (
      C_TARGET : TARGET_FAMILY_TYPE);
    port (
      D_In    : in  std_logic_vector(0 to 31);
      Sel_LSB : in  std_logic_vector(0 to 1);
      D_Out   : out std_logic_vector(0 to 31));
  end component Data_Read_Steering;

  signal byte_Enable_I : std_logic_vector(0 to 3);

  signal sel_LSB            : std_logic_vector(1 downto 0);
  signal sel_Write_Mux_MSB  : std_logic_vector(1 downto 0);

  signal extend_Data_Read_I  : std_logic_vector(0 to C_DATA_SIZE-1);
  signal extend_Data_Write_I : std_logic_vector(0 to C_DATA_SIZE-1);

  signal Data_Write_To_Mux_MSB  : std_logic_vector(0 to C_DATA_SIZE-1);
  signal iByte                  : std_logic;
  signal iDoublet               : std_logic;

  signal Low_Addr : std_logic_vector(0 to 1);

-------------------------------------------------------------------------------
-- Begin architecture
-------------------------------------------------------------------------------

begin  -- architecture IMP

  iByte    <= '1' when Byte    else '0';
  iDoublet <= '1' when Doublet else '0';

  Low_Addr(1) <= Op2_Low(1) xor (Op1_Low(1));
  Low_Addr(0) <= Op2_Low(0) xor (Op1_Low(0)) xor
                 (Op2_Low(1) and (Op1_Low(1)));

  Using_FPGA : if (C_TARGET /= RTL) generate
    
    Data_Size_Is_32 : if (C_DATA_SIZE = 32) generate
    begin
-----------------------------------------------------------------------------
------ Byte Enables
-----------------------------------------------------------------------------
--  Byte_Enable_Handler : process (Byte, Doublet, Low_Addr) is                    
--  begin  -- process Byte_Enable_Handler                                         
--    byte_Enable_I <= (others => '0');                                           
--    if Byte then                                                                
--      case Low_Addr is                                                          
--        when BYTE_0 => byte_Enable_I(BYTE_ENABLE_BYTE_0) <= '1';                
--        when BYTE_1 => byte_Enable_I(BYTE_ENABLE_BYTE_1) <= '1';                
--        when BYTE_2 => byte_Enable_I(BYTE_ENABLE_BYTE_2) <= '1';                
--        when BYTE_3 => byte_Enable_I(BYTE_ENABLE_BYTE_3) <= '1';                
--        when others => null;                                                    
--      end case;                                                                 
--    elsif Doublet then                                                          
--      case Low_Addr(Low_Addr'left) is                                          
--        when '0'    => byte_Enable_I(BYTE_ENABLE_DOUBLET_LOW_TYPE)  <= "11";    
--        when '1'    => byte_Enable_I(BYTE_ENABLE_DOUBLET_HIGH_TYPE) <= "11";    
--        when others => null;                                                    
--      end case;                                                                 
--    else                                                                        
--      byte_Enable_I <= (others => '1');                                         
--    end if;                                                                     
--  end process Byte_Enable_Handler;                                              
-----------------------------------------------------------------------------

      BYTE_0_I : LUT4
        generic map(INIT => X"8A8F")
        port map (
          O  => byte_Enable_I(3),          --[out]
          I0 => Low_Addr(Low_Addr'left),   --[in]
          I1 => Low_Addr(Low_Addr'right),  --[in]
          I2 => iByte,                     --[in]
          I3 => iDoublet                   --[in]
          );
      BYTE_1_I : LUT4
        generic map(INIT => X"0BAB")
        port map (
          O  => byte_Enable_I(2),          --[out]
          I0 => Low_Addr(Low_Addr'left),   --[in]
          I1 => iDoublet,                  --[in]
          I2 => iByte,                     --[in]
          I3 => Low_Addr(Low_Addr'right)   --[in]
          );
      BYTE_2_I : LUT4
        generic map(INIT => X"454F")
        port map (
          O  => byte_Enable_I(1),          --[out]
          I0 => Low_Addr(Low_Addr'left),   --[in]
          I1 => Low_Addr(Low_Addr'right),  --[in]
          I2 => iByte,                     --[in]
          I3 => iDoublet                   --[in]
          );
      BYTE_3_I : LUT4
        generic map(INIT => X"151F")
        port map (
          O  => byte_Enable_I(0),          --[out]
          I0 => Low_Addr(Low_Addr'left),   --[in]
          I1 => Low_Addr(Low_Addr'right),  --[in]
          I2 => iByte,                     --[in]
          I3 => iDoublet                   --[in]
          );

      Byte_Enable <= byte_Enable_I;

      -----------------------------------------------------------------------------
      -- Handles data read bus
      -- With or Without dynamic bus sizing
      -----------------------------------------------------------------------------

      No_Bus_Sizing : if not C_DYNAMIC_BUS_SIZING generate
        extend_Data_Read_I  <= Data_Read;
        extend_Data_Write_I <= Data_Write;
      end generate No_Bus_Sizing;

      Use_Dynamic_Bus_Sizing : if C_DYNAMIC_BUS_SIZING generate

        --  Extend_Data_Read_Sel_LSB_1 : process (Doublet, Low_Addr) is
        --  begin  -- process Extend_Data_Read_Sel_LSB_1
        --    if Doublet then
        --      sel_LSB_1 <= Low_Addr(Low_Addr'left);
        --    else
        --      sel_LSB_1 <= '0';
        --    end if;
        --  end process Extend_Data_Read_Sel_LSB_1;
        --
        --  Extend_Data_Read_Mux_LSB_1 : process (sel_LSB_1, Data_Read) is
        --  begin  -- process Extend_Data_Read_Mux_LSB_1
        --    case sel_LSB_1 is
        --      when '0' =>
        --        extend_Data_Read_I(16 to 23) <= 
        --          Data_Read(16 to 23);
        --      when '1' =>
        --        extend_Data_Read_I(16 to 23) <= 
        --          Data_Read(0 to 7);
        --      when others => null;
        --    end case;
        --  end process Extend_Data_Read_Mux_LSB_1;

        -------------------------------------------------------------------------
        -- Generate the selects for the Read Data steering mux
        -- LUTs implement the following function:
        --
        -- Extend_Data_Read_Sel_LSB : process (Byte, Doublet, Low_Addr) is
        -- begin  -- process Extend_Data_Read_LSB
        --   if Byte then
        --     sel_LSB <= Low_Addr;
        --   elsif Doublet then
        --     sel_LSB <= Low_Addr(Low_Addr'left) & '1';
        --   else
        --     sel_LSB <= "11";
        --   end if;
        -- end process Extend_Data_Read_Sel_LSB;
        --
        -- Read Data Steering Logic function:
        ------------------------------------------------------------------- 
        --  addr        type       desired bus connection    |  mux selects 
        -- A0  A1   Byte Doublet  D(0:15) D(16:23) D(24:31)  |    S0  S1 
        ------------------------------------------------------------------- 
        -- X   X     0     0      D(0:15) D(16:23) D(24:31)  |     1   1 
        -- 0   X     0     1         X    D(0:7)   D(8:15 )  |     0   1 
        -- 1   X     0     1         X    D(16:23) D(24:31)  |     1   1 
        -- 0   0     1     0         X       X     D(0:7)    |     0   0