dplb_interface.vhd

Xilinx软核microblaze源码(VHDL)版本7.10

-------------------------------------------------------------------------------
-- $Id: dplb_interface.vhd,v 1.2 2008/01/16 15:46:49 stefana Exp $
-------------------------------------------------------------------------------
-- dplb_interface.vhd - Entity and architecture
--
--  ***************************************************************************
--  **  Copyright(C) 2006 by Xilinx, Inc. All rights reserved.               **
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--
-------------------------------------------------------------------------------
-- Filename:        dplb_interface.vhd
--
-- Description:     Data side PLB interface
--                  
-- VHDL-Standard:   VHDL'93/02
-------------------------------------------------------------------------------
-- Structure:   
--              dplb_interface.vhd
--
-------------------------------------------------------------------------------
-- Author:          goran
-- Revision:        $Revision: 1.2 $
-- Date:            $Date: 2008/01/16 15:46:49 $
--
-- History:
--   goran  2006-08-11    First Version
--
-------------------------------------------------------------------------------
-- Naming Conventions:
--      active low signals:                     "*_n"
--      clock signals:                          "clk", "clk_div#", "clk_#x" 
--      reset signals:                          "rst", "rst_n" 
--      generics:                               "C_*" 
--      user defined types:                     "*_TYPE" 
--      state machine next state:               "*_ns" 
--      state machine current state:            "*_cs" 
--      combinatorial signals:                  "*_com" 
--      pipelined or register delay signals:    "*_d#" 
--      counter signals:                        "*cnt*"
--      clock enable signals:                   "*_ce" 
--      internal version of output port         "*_i"
--      device pins:                            "*_pin" 
--      ports:                                  - Names begin with Uppercase 
--      processes:                              "*_PROCESS" 
--      component instantiations:               "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;

library Microblaze_v7_10_a;
use Microblaze_v7_10_a.MicroBlaze_Types.all;

-------------------------------------------------------------------------------
-- Port declarations
-------------------------------------------------------------------------------

entity DPLB_Interface is
  generic (
    C_DPLB_WIDTH          : natural := 32;
    C_DELAYED_DATA_STROBE : boolean := false;
    C_OUTPUT_DFFS         : boolean := false
    );
  port (
    -- global signals
    Clk   : in std_logic;
    Reset : in std_logic;

    -- PLB signals
    DPLB_M_ABort      : out std_logic;
    DPLB_M_ABus       : out std_logic_vector(0 to 31);
    DPLB_M_UABus      : out std_logic_vector(0 to 31);
    DPLB_M_BE         : out std_logic_vector(0 to (C_DPLB_WIDTH-1)/8);
    DPLB_M_busLock    : out std_logic;
    DPLB_M_lockErr    : out std_logic;
    DPLB_M_MSize      : out std_logic_vector(0 to 1);
    DPLB_M_priority   : out std_logic_vector(0 to 1);
    DPLB_M_rdBurst    : out std_logic;
    DPLB_M_request    : out std_logic;
    DPLB_M_RNW        : out std_logic;
    DPLB_M_size       : out std_logic_vector(0 to 3);
    DPLB_M_TAttribute : out std_logic_vector(0 to 15);
    DPLB_M_type       : out std_logic_vector(0 to 2);
    DPLB_M_wrBurst    : out std_logic;
    DPLB_M_wrDBus     : out std_logic_vector(0 to C_DPLB_WIDTH-1);

    DPLB_MBusy        : in std_logic;
    DPLB_MRdErr       : in std_logic;
    DPLB_MWrErr       : in std_logic;
    DPLB_MIRQ         : in std_logic;
    DPLB_MWrBTerm     : in std_logic;
    DPLB_MWrDAck      : in std_logic;
    DPLB_MAddrAck     : in std_logic;
    DPLB_MRdBTerm     : in std_logic;
    DPLB_MRdDAck      : in std_logic;
    DPLB_MRdDBus      : in std_logic_vector(0 to C_DPLB_WIDTH-1);
    DPLB_MRdWdAddr    : in std_logic_vector(0 to 3);
    DPLB_MRearbitrate : in std_logic;
    DPLB_MSSize       : in std_logic_vector(0 to 1);
    DPLB_MTimeout     : in std_logic;

    -- Local Bus signals
    MEM_DataBus_Access      : in std_logic;
    MEM_DataBus_Addr        : in DATA_TYPE;
    MEM_DataBus_Write       : in std_logic;
    MEM_DataBus_Write_Data  : in DATA_TYPE;
    MEM_DataBus_Byte_Enable : in DATA_BE_TYPE;
    MEM_DataBus_Read        : in std_logic;

    WB_DPLB_Data_Strobe : out std_logic;
    WB_DPLB_Read_Data   : out DATA_TYPE;

    -- other signals
    MEM_DataBus_Drop_Request   : in  std_logic;
    MEM_DataBus_Enable_BusLock : in  std_logic;
    MEM_DPLB_Data_Strobe       : out std_logic;
    MEM_DPLB_Exception         : out std_logic
    );

end entity DPLB_Interface;

architecture IMP of DPLB_Interface is

  signal mem_access_completed : std_logic;

  signal active_access    : std_logic;
  signal active_access_d1 : std_logic;

  signal active_access_d2 : std_logic;

  signal bus_access_ended : std_logic;

  -- local signals for the mirroring
  signal dplb_m_be_i     : std_logic_vector(0 to 3);
  signal dplb_m_wrdbus_i : std_logic_vector(0 to 31);

-------------------------------------------------------------------------------
-- Begin architecture
-------------------------------------------------------------------------------
begin
  -----------------------------------------------------------------------------
  -- Constant values on PLB signals
  -----------------------------------------------------------------------------  
  DPLB_M_ABort      <= '0';             -- Abort is not used and is not
                                        -- available in Xilinx subset of PLB v4.6
  DPLB_M_UABus      <= (others => '0');  -- Not used in Xilinx subset of PLB v4.6
  DPLB_M_busLock    <= '0';    -- Not used in Xilinx subset of PLB v4.6
  DPLB_M_lockErr    <= '0';    -- Not used in Xilinx subset of PLB v4.6
  DPLB_M_priority   <= "00";   -- Not used in Xilinx subset of PLB v4.6
  DPLB_M_rdBurst    <= '0';    -- Not used by MicroBlaze, no burst handling
  DPLB_M_TAttribute <= (others => '0');  -- Not used in Xilinx subset of PLB v4.6
  DPLB_M_type       <= "000";  -- Not used in Xilinx subset of PLB v4.6
  DPLB_M_wrBurst    <= '0';    -- Not used by MicroBlaze, no burst handling

  DPLB_M_MSize <= "00";    -- MicroBlaze only do 32-bit data transfers
  DPLB_M_size  <= "0000";               -- MicroBlaze only request 32-bit
                                        -- single beat transfers

  -----------------------------------------------------------------------------
  -- Just drive the PLB signals
  -- no requirement to drive to "0" while not requesting access
  -----------------------------------------------------------------------------
  No_Extra_DFFs : if (not C_OUTPUT_DFFS) generate
    DPLB_M_ABus            <= MEM_DataBus_Addr;
    DPLB_M_RNW             <= MEM_DataBus_Read;
    dplb_m_be_i            <= MEM_DataBus_Byte_Enable;
    dplb_m_wrdbus_i        <= MEM_DataBus_Write_Data;
  end generate No_Extra_DFFs;

  Add_Output_DFFs: if (C_OUTPUT_DFFS) generate

    Output_DFFs : process (Clk) is
    begin  -- process Output_DFFs
      if Clk'event and Clk = '1' then   -- rising clock edge
        if Reset = '1' then             -- synchronous reset (active high)
          DPLB_M_ABus            <= (others => '0');
          DPLB_M_RNW             <= '0';
          dplb_m_be_i            <= (others => '0');
          dplb_m_wrdbus_i        <= (others => '0');
        else
          DPLB_M_ABus            <= MEM_DataBus_Addr;
          DPLB_M_RNW             <= MEM_DataBus_Read;
          dplb_m_be_i            <= MEM_DataBus_Byte_Enable;
          dplb_m_wrdbus_i        <= MEM_DataBus_Write_Data;
        end if;
      end if;
    end process Output_DFFs;
    
  end generate Add_Output_DFFs;

  -----------------------------------------------------------------------------
  -- Handling the 32 bit widths
  -----------------------------------------------------------------------------
  DPLB_M_wrDBus(0 to 31) <= dplb_m_wrdbus_i;
  DPLB_M_BE(0 to 3)      <= dplb_m_be_i;

  -----------------------------------------------------------------------------
  -- Handling 64/128 widths
  -----------------------------------------------------------------------------
  Using_64bitBus : if (C_DPLB_WIDTH = 64) generate
    DPLB_M_BE(4 to 7)       <= dplb_m_be_i;
    DPLB_M_wrDBus(32 to 63) <= dplb_m_wrdbus_i;    
  end generate Using_64bitBus;
  Using_128bitBus: if (C_DPLB_WIDTH = 128) generate
    DPLB_M_BE(8 to 15)       <= dplb_m_be_i & dplb_m_be_i;
    DPLB_M_wrDBus(64 to 127) <= dplb_m_wrdbus_i & dplb_m_wrdbus_i;        
  end generate Using_128bitBus;
  -----------------------------------------------------------------------------
  -- Arbitration signalling
  -----------------------------------------------------------------------------
  PLB_Request : process (Clk) is
  begin  -- process PLB_Request
    if Clk'event and Clk = '1' then     -- rising clock edge
      if Reset = '1' then               -- synchronous reset (active high)
        DPLB_M_request   <= '0';
        active_access    <= '0';
        active_access_d1 <= '0';
      else
        active_access_d1 <= active_access;
        active_access_d2 <= active_access_d1;
        -- A new request is request and Cache or LMB has not already responded
        -- and the transfer is not finished
        -- When the extra delay is active the active_access_d2 shall be used to
        -- avoid initialization of another access cycle due to the internal 
        -- decoding/decision latency.
        if ((MEM_DataBus_Access = '1') and (MEM_DataBus_Drop_Request = '0')
            and (active_access_d1 = '0')
            and ( (active_access_d2 = '0') or (not C_DELAYED_DATA_STROBE) ) ) then
          DPLB_M_request <= '1';
          active_access  <= '1';
        end if;
        -- Timeout => end request and signalling databus exception
        if (DPLB_MTimeout = '1') then
          DPLB_M_request <= '0';
          active_access  <= '0';
        end if;
        -- Address phase is acknowledge
        if (DPLB_MAddrAck = '1') then
          DPLB_M_request <= '0';
        end if;

        if ((DPLB_MRdDAck = '1') or (DPLB_MWrDAck = '1')) then          
          active_access  <= '0';       
        end if;
      end if;
    end if;

  end process PLB_Request;

  -----------------------------------------------------------------------------
  -- Data PLB access completion
  -----------------------------------------------------------------------------

  MEM_DPLB_Data_Strobe <= bus_access_ended;

  access_completion_DFF : process (Clk)
  begin
    if Clk'event and Clk = '1' then     -- rising clock edge
      if Reset = '1' then
        WB_DPLB_Data_Strobe  <= '0';
        WB_DPLB_Read_Data    <= (others => '0');
        MEM_DPLB_Exception   <= '0';
        mem_access_completed <= '0';
      else
        mem_access_completed <= DPLB_MRdDAck or DPLB_MWrDAck or DPLB_MTimeout;
        WB_DPLB_Data_Strobe  <= bus_access_ended;
        MEM_DPLB_Exception   <= DPLB_MRdErr or DPLB_MWrErr or DPLB_MTimeout;
        if DPLB_MRdDAck = '1' then
          WB_DPLB_Read_Data <= DPLB_MRdDBus(0 to 31);
        end if;
      end if;
    end if;
  end process access_completion_DFF;

  -----------------------------------------------------------------------------
  -- Delaying Data_strobe one clock cycle compared to the exception signal
  -- This is used by the area version when DataBus exception is implemented to
  -- be able to get time to generate an exception without the pipe is moving
  -----------------------------------------------------------------------------
  Delaying_Data_strobe : if (C_DELAYED_DATA_STROBE) generate
    Delay_Strobe : process (Clk) is
    begin  -- process Delay_Strobe
      if Clk'event and Clk = '1' then   -- rising clock edge
        if Reset = '1' then             -- synchronous reset (active high)
          bus_access_ended <= '0';
        else
          bus_access_ended <= mem_access_completed;
        end if;
      end if;
    end process Delay_Strobe;
  end generate Delaying_Data_strobe;

  No_Delaying_of_Data_Strobe: if (not C_DELAYED_DATA_STROBE) generate
    bus_access_ended <= mem_access_completed;    
  end generate No_Delaying_of_Data_Strobe;


end architecture IMP;