debug_gti.vhd

Xilinx软核microblaze源码(VHDL)版本7.10

  end process Reg_access_Delay;

  -----------------------------------------------------------------------------
  -- Do the TDO output mux
  -----------------------------------------------------------------------------
  TDO_Mux : process (TDO_Status_Reg, Status_Reg_En, TDO_Data_Reg, Data_Read_Reg_En, Config_Reg_En, TDO_Config_Word) is
  begin  -- process TDO_Mux
    if (Status_Reg_En = '1') then
      TDO <= TDO_Status_Reg;
    elsif (Data_Read_Reg_En = '1') then
      TDO <= TDO_Data_Reg;
    elsif (Config_Reg_En = '1') then      
      TDO <= TDO_Config_Word;
    else
      TDO <= '0';
    end if;
  end process TDO_Mux;

  -----------------------------------------------------------------------------
  -- Instanciate all PC breakpoints
  -----------------------------------------------------------------------------

  Enable_PC_Brks : process (Reg_En) is
  begin  -- process Enable_PC_Brks
    which_pc <= (others => '0');        --default
    if (Reg_En(0) = '1') then
      for I in 0 to C_Nr_of_Brks-1 loop
        if (I = to_integer(unsigned(Reg_En(1 to 4)))) then
          which_pc(I) <= '1';
        end if;
      end loop;  -- I
    end if;
  end process Enable_PC_Brks;

  Using_PC_Breakpoints : if (C_NUMBER_OF_PC_BRK > 0) generate
    
    All_PC_Brks : for I in 0 to C_NUMBER_OF_PC_BRK-1 generate
      address_hit_I : address_hit
        generic map (
          C_TARGET => C_TARGET,
          C_FIRST  => (I = 0),
          No_Bits  => C_DATA_SIZE)      -- [natural]
        port map (
          Address       => PC_OF,  -- [in  std_logic_vector(0 to No_Bits-1)]
          Armed         => armed,       -- [in  std_logic]
          TClk          => TClk,        -- [in  std_logic]
          TDI           => TDI,         -- [in  std_logic]
          SRL16_En      => which_pc(I),  -- [in  std_logic_vector(0 to ((No_Bits+7)/8)-1)]
          Single_Step_N => '1',  -- [in  std_logic]
          Hit           => dbg_hit_i(I));   -- [out std_logic]
    end generate All_PC_Brks;
  end generate Using_PC_Breakpoints;
  
  -----------------------------------------------------------------------------
  -- Insert logic for stopping and single-stepping
  -----------------------------------------------------------------------------
  No_PC_Breakpoints : if (C_NUMBER_OF_PC_BRK = 0) generate
    dbg_hit_i(C_NUMBER_OF_RD_ADDR_BRK + C_NUMBER_OF_WR_ADDR_BRK) <= not single_Step_N;
  end generate No_PC_Breakpoints;

  -----------------------------------------------------------------------------
  -- Insert all Read Address Watchpoints
  -----------------------------------------------------------------------------
  Using_Rd_Addr_Breakpoints : if (C_NUMBER_OF_RD_ADDR_BRK > 0) generate

    WB_Data_Addr_DFF: process (Clk) is
    begin  -- process WB_Data_Addr_DFF
      if Clk'event and Clk = '1' then   -- rising clock edge
        if Reset = '1' then             -- synchronous reset (active high)
          WB_Data_Addr <= (others => '0');
        elsif (MEM_PipeRun) then
          WB_Data_Addr <= MEM_Data_Addr;          
        end if;
      end if;
    end process WB_Data_Addr_DFF;

    WB_ReadInstr_Done: process (Clk) is
    begin  -- process WB_ReadInstr_Done
      if Clk'event and Clk = '1' then   -- rising clock edge
        if Reset = '1' then             -- synchronous reset (active high)
          WB_Read_Instr <= '0';
        else
          WB_Read_Instr <= MEM_Read_Instr and MEM_DReady;         
        end if;
      end if;
    end process WB_ReadInstr_Done;

    All_Rd_Addr_Breakpoints : for I in 0 to C_NUMBER_OF_RD_ADDR_BRK - 1 generate
      address_data_hit_2 : address_data_hit
        generic map (
          C_TARGET => C_TARGET,         -- [TARGET_FAMILY_TYPE]
          No_Bits  => C_DATA_SIZE)      -- [natural]
        port map (
          Address  => WB_Data_Addr,  -- [in  std_logic_vector(0 to No_Bits-1)]
          Data     => WB_DataBus_Steered_Read_Data,  -- [in  std_logic_vector(0 to No_Bits-1)]
          Armed    => WB_Read_Instr,    -- [in  std_logic]
          TClk     => TClk,             -- [in  std_logic]
          TDI    => TDI,              -- [in  std_logic]
          SRL16_En => which_pc(I+C_NUMBER_OF_PC_BRK),  -- [in  std_logic]
          Hit      => dbg_hit_i(I+C_NUMBER_OF_PC_BRK));  -- [out std_logic]

    end generate All_Rd_Addr_Breakpoints;

  end generate Using_Rd_Addr_Breakpoints;

  Using_Wr_Addr_Breakpoints : if (C_NUMBER_OF_WR_ADDR_BRK > 0) generate

    All_Wr_Addr_Breakpoints : for I in 0 to C_NUMBER_OF_WR_ADDR_BRK - 1 generate
      address_data_hit_1 : address_data_hit
        generic map (
          C_TARGET => C_TARGET,         -- [TARGET_FAMILY_TYPE]
          No_Bits  => C_DATA_SIZE)      -- [natural]
        port map (
          Address  => MEM_Data_Addr,  -- [in  std_logic_vector(0 to No_Bits-1)]
          Data     => MEM_Data_Write,  -- [in  std_logic_vector(0 to No_Bits-1)]
          Armed    => MEM_Write_Instr,  -- [in  std_logic]
          TClk     => TClk,             -- [in  std_logic]
          TDI      => TDI,              -- [in  std_logic]
          SRL16_En => which_pc(I+C_NUMBER_OF_PC_BRK + C_NUMBER_OF_RD_ADDR_BRK),  -- [in  std_logic]
          Hit      => dbg_hit_i(I + C_NUMBER_OF_PC_BRK + C_NUMBER_OF_RD_ADDR_BRK)  -- [out std_logic]
          );
    end generate All_Wr_Addr_Breakpoints;
  end generate Using_Wr_Addr_Breakpoints;

  -----------------------------------------------------------------------------
  -- Creating one signal for all PC breakpoints and one signal for all watchpoints
  -----------------------------------------------------------------------------
  Fixing_PC_Brk : process (dbg_hit_i) is
    variable pc_brk_temp    : std_logic;
    variable watchpoint_brk_temp : std_logic;
  begin  -- process Fixing_PC_Brk    
    if (C_NUMBER_OF_PC_BRK = 0) then
      pc_brk <= dbg_hit_i(C_NUMBER_OF_RD_ADDR_BRK + C_NUMBER_OF_WR_ADDR_BRK);
    else
      pc_brk_temp := '0';
      for I in 0 to C_NUMBER_OF_PC_BRK - 1 loop
        pc_brk_temp := pc_brk_temp or dbg_hit_i(I);
      end loop;  -- I
      pc_brk <= pc_brk_temp;
    end if;

    watchpoint_brk_temp := '0';
    
    if (C_NUMBER_OF_RD_ADDR_BRK > 0) then
      for I in 0 to C_NUMBER_OF_RD_ADDR_BRK-1 loop
        watchpoint_brk_temp := watchpoint_brk_temp or dbg_hit_i(I+C_NUMBER_OF_PC_BRK);
      end loop;  -- I
    end if;

    if (C_NUMBER_OF_WR_ADDR_BRK > 0) then
      for I in 0 to C_NUMBER_OF_WR_ADDR_BRK-1 loop
        watchpoint_brk_temp := watchpoint_brk_temp or dbg_hit_i(I + C_NUMBER_OF_PC_BRK + C_NUMBER_OF_RD_ADDR_BRK);        
      end loop;  -- I
    end if;
    watchpoint_brk <= watchpoint_brk_temp;
    
  end process Fixing_PC_Brk;

  -----------------------------------------------------------------------------
  -- Watchpoint breaks needs to be hold until the instruction has moved into
  -- the OF stage since the actual dbg_hit can dissappear when the pipeline is
  -- moving without the OF stage is moving
  -- Also need to save the dbg_hit_i
  -----------------------------------------------------------------------------
  Holding_Watchpoint_Brk : process (Clk) is
  begin  -- process Holding_Watchpoint_Brk
    if Clk'event and Clk = '1' then     -- rising clock edge
      if Reset = '1' then               -- synchronous reset (active high)
        watchpoint_brk_hold <= '0';
        dbg_hit_hold_i      <= (others => '0');
      else
        if (watchpoint_brk = '1') then
          watchpoint_brk_hold <= '1';
          dbg_hit_hold_i      <= dbg_hit_i;
        end if;
        if (of_PipeRun) then
          watchpoint_brk_hold <= '0';
        end if;
      end if;
    end if;
  end process Holding_Watchpoint_Brk;

  dbg_brk <= pc_brk or watchpoint_brk or watchpoint_brk_hold;
  
  EX_Dbg_hit_DFF : process (Clk) is
  begin  -- process EX_Dbg_hit
    if Clk'event and Clk = '1' then     -- rising clock edge
      if Reset_b then                   -- synchronous reset (active high)
        ex_dbg_hit <= (others => '0');
      elsif (OF_PipeRun) then                
        if (pc_brk = '1') or (watchpoint_brk = '1') then
          ex_dbg_hit <= (others => '0');
          for I in 0 to C_NR_OF_BRKS - 1 loop
            ex_dbg_hit(I) <= dbg_hit_i(I);
          end loop;
        end if;
        if (watchpoint_brk_hold = '1') then
          ex_dbg_hit <= (others => '0');
          for I in C_NUMBER_OF_PC_BRK to C_NR_OF_BRKS - 1 loop
            ex_dbg_hit(I) <= dbg_hit_hold_i(I);            
          end loop;  -- I
        end if;
      end if;
    end if;
  end process EX_Dbg_hit_DFF;

  MEM_Dbg_Hit_DFF: process (Clk) is
  begin  -- process MEM_Dbg_Hit_DFF
    if Clk'event and Clk = '1' then     -- rising clock edge
      if Reset_b then               -- synchronous reset (active high)
        mem_dbg_hit <= (others => '0');
      elsif (EX_PipeRun) then
        mem_dbg_hit <= ex_dbg_hit;        
      end if;
    end if;
  end process MEM_Dbg_Hit_DFF;

  WB_Dbg_Hit_DFF: process (Clk) is
  begin  -- process WB_Dbg_Hit_DFF
    if Clk'event and Clk = '1' then     -- rising clock edge
      if Reset_b then               -- synchronous reset (active high)
        wb_dbg_hit <= (others => '0');
      elsif (MEM_PipeRun) then
        wb_dbg_hit <= mem_dbg_hit;        
      end if;
    end if;
  end process WB_Dbg_Hit_DFF;

  Active_Dbg_PC_Hit: process (Clk) is
  begin  -- process Active_Dbg_PC_Hit
    if Clk'event and Clk = '1' then     -- rising clock edge
      if Reset_b then               -- synchronous reset (active high)
        dbg_hit <= (others => '0');
      else
        if (WB_Halted) then
          dbg_hit <= (others => '0');                      
          dbg_hit(wb_dbg_hit'range) <= wb_dbg_hit;
        end if;
      end if;
    end if;
  end process Active_Dbg_PC_Hit;
  
  -----------------------------------------------------------------------------
  -- Need to stop the CPU when a Breakpoint is reached
  -----------------------------------------------------------------------------

  single_Step_CPU   <= free_running or start_single_step or continue_from_brk when not reset_b else '1';

  Dbg_Inhibit_EX_i <= '0';
  
  Dbg_Stop_Instr_Fetch <= Dbg_Stop_Instr_Fetch_i when not WB_Halted else '1';

  External_Dbg_Stop_Handle: process (Clk) is
    variable dbg_stop_1 : std_logic;
  begin  -- process External_Dbg_Stop_Handle
    if Clk'event and Clk = '1' then     -- rising clock edge
      if Reset = '1' then               -- synchronous reset (active high)
        dbg_stop_i <= false;
        dbg_stop_1 := '0';
      else
        --detecting a rising edge on dbg_stop
        if ((dbg_stop) = '0' and (dbg_stop_1) = '1') then
          -- Force a hw breakpoint into the EX stage
          dbg_stop_i <= true;
        end if;
        -- When the halted instruction is reached WB stage and causing a
        -- breakpoint, deassert the dbg_stop_i signal
        if (WB_Halted) then
          dbg_stop_i <= false;
        end if;
        dbg_stop_1 := Dbg_Stop;
      end if;
    end if;
  end process External_Dbg_Stop_Handle;
  
  
  EX_Breakpoint_DFF : process (Clk) is
  begin  -- process EX_Breakpoint_DFF
    if Clk'event and Clk = '1' then          -- rising clock edge
      if reset_b then                        -- synchronous reset (active true)
        EX_Dbg_PC_Hit             <= false;
        ex_dbg_pc_hit_single_step <= false;  -- Added to detect if single_step
                                             -- was causing the break
      elsif (OF_PipeRun) and (
        ((dbg_brk = '1') and (Dbg_Stop_Instr_Fetch_i = '0')) or
        (single_Step_N = '0') or dbg_stop_i) then
        EX_Dbg_PC_Hit             <= true;
        ex_dbg_pc_hit_single_step <= (single_Step_N = '0');
      elsif (EX_PipeRun) then
        -- If EX_Dbg_PC_Hit was raised by XMD (Single_Step_N = '0') then we
        -- must hold the EX_Dbg_PC_Hit until the exception is acknowledged
        -- If a breakpoint was causing the break then we remove the signal when
        -- the instruction slot is moved into MEM
        if (ex_dbg_pc_hit_single_step) then
          if EX_Exception_Taken then
            EX_Dbg_PC_Hit             <= false;
            ex_dbg_pc_hit_single_step <= false;
          end if;
        else
          EX_Dbg_PC_Hit <= false;
        end if;
      end if;
    end if;
  end process EX_Breakpoint_DFF;

  Dbg_freeze_DFF : process (Clk) is
  begin  -- process Dbg_freeze_DFF
    if Clk'event and Clk = '1' then     -- rising clock edge      
      if reset_b then                   -- synchronous reset (active true)
        dbg_freeze_i           <= false;
        Dbg_Stop_Instr_Fetch_i <= '0';
        dbg_state_i            <= false;
      elsif (WB_Halted) then
        dbg_freeze_i           <= true;
        Dbg_Stop_Instr_Fetch_i <= '1';
        dbg_state_i            <= true;
      elsif (IF_Debug_Ready_i = '1') then  -- Execute inserted instruction
        dbg_freeze_i <= false;        
      elsif (single_Step_CPU = '1') and (dbg_state_i) then
        Dbg_Stop_Instr_Fetch_i <= '0';  -- Open up instruction fetches
        dbg_state_i            <= false;
        dbg_freeze_i           <= false;
      end if;
      if (free_running = '1') then
        dbg_state_i <= false;
      end if;
      if (continue_from_brk = '1') then
        Dbg_Stop_Instr_Fetch_i <= '0';
        dbg_state_i            <= false;
        dbg_freeze_i           <= false;
      end if;
    end if;
  end process Dbg_freeze_DFF;

  Dbg_Freeze <= dbg_freeze_i or wb_halted;
  Dbg_State  <= dbg_state_i or wb_halted;
    
end architecture IMP;