debug_gti.vhd

Xilinx软核microblaze源码(VHDL)版本7.10

      end if;
    end if;
  end process Using_full_32_bit_immediates;

  Delay_slot_instruction : process (Clk) is
  begin  -- process Delay_slot_instruction
    if Clk'event and Clk = '1' then     -- rising clock edge
      if Reset_b then                     -- synchronous reset (active true)
        delay_slot_instr <= '0';
      elsif WB_Halted then
        if (WB_DelaySlot_Instr) then
          delay_slot_instr <= '1';
        else
          delay_slot_instr <= '0';
        end if;
      end if;
    end if;
  end process Delay_slot_instruction;

  Status_Reg_Handle : process (TCLK) is
    variable stop_CPU_1 : std_logic;
    variable dbg_hit_1   : std_logic_vector(0 to 15);
  begin  -- process Status_Reg_Handle
    if TCLK'event and TCLK = '1' then   -- rising clock edge
      if (Capture = '1') then
        status_Reg(16) <= stop_CPU_1;
        if (reset_b) then
          status_Reg(17) <= '1';
        else
          status_Reg(17) <= '0';
        end if;
        status_Reg(18)      <= Full_32_bit;
        status_Reg(19)      <= delay_slot_instr;
        status_Reg(20)      <= Full_32_bit_1;
        status_Reg(21)      <= FSL_Stalled;
        status_Reg(22)      <= Memory_Stalled;
        status_Reg(0 to 15) <= dbg_hit_1;
      end if;
      stop_CPU_1 := dbg_Stop_Instr_Fetch_i;
      dbg_hit_1   := dbg_hit;
    end if;
  end process Status_Reg_Handle;

    -- TDO_Status_Reg_for_simulation
    -- pragma translate_off
    TDO_Status_Reg_for_simulation: process (shift_Count) is
    begin  -- process Process_Only_For_Simulation
      if (unsigned(shift_Count) < status_Reg'length) then
        -- pragma translate_on
        TDO_Status_Reg <= status_Reg(to_integer(unsigned(shift_Count)));
        -- pragma translate_off
      else       
        TDO_Status_Reg <= '0';
      end if;
    end process TDO_Status_Reg_for_simulation;
    -- pragma translate_on

  -----------------------------------------------------------------------------
  -- Shifting in data into a 32-bit shift register
  -----------------------------------------------------------------------------
  Shift_DataIn_Handle : process (TClk) is
  begin  -- process Shift_DataIn_Handle
    if TClk'event and TClk = '1' then   -- rising clock edge
      shift_datain(0 to shift_datain'right-1) <= shift_datain(1 to shift_datain'right);
      shift_datain(shift_datain'right)        <= TDI;
    end if;
  end process Shift_DataIn_Handle;

  -----------------------------------------------------------------------------
  -- Handling the Control Register
  -----------------------------------------------------------------------------
  Control_Reg_Handle : process (Update) is
  begin  -- process Control_Reg_Handle
    if Update'event and Update = '1' then  -- rising clock edge
      if Control_Reg_En = '1' then
        control_Reg <= shift_datain(shift_datain'right+1-control_Reg'length to shift_datain'right);
      end if;
    end if;
  end process Control_Reg_Handle;

  Single_Step_Control_Reg_Handle : process (Update,start_single_step) is
  begin  -- process Single_Step_Control_Reg_Handle
    if (start_single_step = '1') then
      single_Step_TClk <= '0';
    elsif Update'event and Update = '1' then   -- rising clock edge
      if Control_Reg_En = '1' then
        single_Step_TClk <= shift_datain(shift_datain'right - control_Reg'length + 1 + single_step_pos_C);
      end if;
    end if;
  end process Single_Step_Control_Reg_Handle;

  Continue_from_brk_Control_Reg_Handle : process (Update,continue_from_brk) is
  begin  -- process Continue_from_brk_Control_Reg_Handle
    if (continue_from_brk = '1') then
      continue_from_brk_TClk <= '0';
    elsif Update'event and Update = '1' then   -- rising clock edge
      if Control_Reg_En = '1' then
        continue_from_brk_TClk <= shift_datain(shift_datain'right - control_Reg'length + 1 + continue_pos_C);
      end if;
    end if;
  end process Continue_from_brk_Control_Reg_Handle;

  armed                 <= control_Reg(0);
  Dbg_Disable_Interrupt <= (control_reg(dis_intr_pos_C) = '1');

  free_running <= not armed;
  
  Detect_single_step_cmd : process (Clk) is
    variable prev   : std_logic;
    variable prev_1 : std_logic;
  begin  -- process Detect_single_step_cmd
    if Clk'event and Clk = '1' then     -- rising clock edge
      if reset_b then                   -- synchronous reset (active high)
        prev              := '0';
        prev_1            := '0';
        start_single_cmd  <= '0';
      else        
        start_single_cmd <= prev and not prev_1;
        prev_1 := prev;
        prev   := single_Step_TClk;
      end if;
    end if;
  end process Detect_single_step_cmd;

  single_step_DFF : process (Clk) is
  begin  -- process single_step_DFF
    if Clk'event and Clk = '1' then     -- rising clock edge
      if reset_b then                   -- synchronous reset (active high)
        single_Step_N     <= '1';
        start_single_step <= '0';
        single_step_count <= "00";
      else        
        if (start_single_cmd) = '1' then
          start_single_step <= '1';
          single_step_count <= control_reg(single_value_pos_C to single_value_pos_C+1);
        end if;

        if (OF_PipeRun) then
          single_step_count <= std_logic_vector(unsigned(single_step_count) - 1);
          if (start_single_step = '1') and (single_step_count = "00") then
            start_single_step <= '0';
            single_Step_N     <= '0';
          else
            single_Step_N <= '1';
          end if;
        end if;
      end if;
    end if;
  end process single_step_DFF;

--  single_step_N <= '1';
  
  Continue_from_Brk_DFF : process (Clk) is
    variable prev   : std_logic;
    variable prev_1 : std_logic;
  begin  -- process Continue_from_Brk_DFF
    if Clk'event and Clk = '1' then     -- rising clock edge
      if Reset_b then                   -- synchronous reset (active high)
        prev              := '0';
        prev_1            := '0';
        continue_from_brk <= '0';
      else
        continue_from_brk <= prev and not prev_1;
        prev_1            := prev;
        prev              := continue_from_brk_TClk;
      end if;
    end if;
  end process Continue_from_Brk_DFF;

  -----------------------------------------------------------------------------
  -- Handling the Instr_Insert_Reg
  -- Can't assume that TCK is slower than CLK
  -----------------------------------------------------------------------------
  Instr_Insert_Reg_Handle : process (TClk) is
    variable tmp : std_logic := '0';
  begin  -- process Instr_Insert_Reg_Handle
    if TClk'event and TClk = '1' then   -- rising clock edge
      Instr_Insert_Reg_En_1 <= Instr_Insert_Reg_En;
      if Instr_Insert_Reg_En = '1' then
        if (shift_Count(4 downto 0) = "11110") then
          New_Dbg_Instr_TCK <= '1';
        else
          New_Dbg_Instr_TCK <= '0';
        end if;
      else
        New_Dbg_Instr_TCK <= '0';
      end if;
    end if;
  end process Instr_Insert_Reg_Handle;

  New_Instr_Reg_TCK_Handle : process (TClk) is
  begin  -- process New_Instr_Reg_TCK_Handle
    if TClk'event and TClk = '1' then   -- rising clock edge
      New_Dbg_Instr2_TCK <= '0';
      if New_Dbg_Instr_TCK = '1' then
        New_Instr_Reg_TCK  <= shift_datain(1 to 31) & TDI;
        New_Dbg_Instr2_TCK <= '1';
      end if;
    end if;
  end process New_Instr_Reg_TCK_Handle;

  IF_Debug_Instr <= New_Instr_Reg_TCK;

  IF_Debug_Ready_Handle : process (Clk) is
  begin  -- process IF_Debug_Ready_Handle
    if Clk'event and Clk = '1' then     -- rising clock edge
      if Reset_b then                   -- synchronous reset (active true)
        New_Dbg_Instr_CLK  <= '0';
        New_Dbg_Instr2_CLK <= '0';
        IF_Debug_Ready_i   <= '0';
      else
        New_Dbg_Instr_CLK  <= New_Dbg_Instr2_TCK;
        New_Dbg_Instr2_CLK <= New_Dbg_Instr_CLK;
        IF_Debug_Ready_i   <= not New_Dbg_Instr2_CLK and New_Dbg_Instr_CLK;
      end if;
    end if;
  end process IF_Debug_Ready_Handle;

  IF_Debug_Ready <= IF_Debug_Ready_i;

  First_Instruction_to_execute_Handle : process (Clk) is
    variable tmp : std_logic;
  begin  -- process First_Instruction_to_execute_Handle
    if Clk'event and Clk = '1' then     -- rising clock edge
      if Reset_b then                   -- synchronous reset (active true)
        Start_Dbg_Exec <= '0';
        tmp            := '0';
      else
--        Start_Dbg_Exec <= tmp;
        Start_Dbg_Exec <= IF_Debug_Ready_i;
        tmp            := IF_Debug_Ready_i;
      end if;
    end if;
  end process First_Instruction_to_execute_Handle;

  Data_read_reg_Handle : process (TClk) is
  begin  -- process Data_read_reg_Handle
    if TClk'event and TClk = '1' then   -- rising clock edge
      if (Capture = '1') then
        data_read_reg <= data_rd_reg;
      end if;
    end if;
  end process Data_read_reg_Handle;

--  TDO_Data_Reg <= data_read_reg(0);
    -- TDO_Data_Reg_for_simulation
    -- pragma translate_off
    TDO_Data_Reg_for_simulation: process (shift_Count) is
    begin  -- process Process_Only_For_Simulation
      if (unsigned(shift_Count) < data_read_reg'length) then
        -- pragma translate_on
        TDO_Data_Reg <= data_read_reg(to_integer(unsigned(shift_Count)));
        -- pragma translate_off
      else       
        TDO_Data_Reg <= '0';
      end if;
    end process TDO_Data_Reg_for_simulation;
    -- pragma translate_on

  data_rd_reg_handle : process (Clk) is
  begin  -- process data_rd_reg_handle
    if Clk'event and Clk = '1' then     -- rising clock edge
      if Reset_b then                   -- synchronous reset (active high)
        data_rd_reg             <= (others => '0');
        read_pc                 <= '0';
        Instr_Insert_Reg_En_Clk <= '0';
        Command_Reg_Rst         <= '0';
      else
        Command_Reg_Rst         <= '0';
        Instr_Insert_Reg_En_Clk <= Instr_Insert_Reg_En;
        if (read_register_PC_1 = '1') then
          data_rd_reg(0 to C_DATA_SIZE-1) <= WB_PC;
          data_rd_reg(C_DATA_SIZE)        <= WB_PC_Valid or Dbg_Inhibit_EX_i;
          read_pc                         <= '1';
          Command_Reg_Rst                 <= '1';
        end if;
        if (read_register_MSR_1 = '1') then
          data_rd_reg                   <= (others => '0');
          read_pc                       <= '0';
          data_rd_reg(MSR_REG_POS_TYPE) <= WB_MSR;
          Command_Reg_Rst               <= '1';
        end if;
        if (dbg_state_i) then
          read_pc <= '0';
          if (WB_GPR_Wr_Dbg) then
            data_rd_reg(0 to C_DATA_SIZE-1) <= WB_Fwd;
            data_rd_reg(C_DATA_SIZE)        <= '1';
          end if;
        end if;
      end if;
    end if;
  end process data_rd_reg_handle;

  -----------------------------------------------------------------------------
  -- Handling the Command Register
  -----------------------------------------------------------------------------
  Command_Reg_Handle : process (Update, Command_Reg_Rst) is
  begin  -- process Command_Reg_Handle
    if (Command_Reg_Rst = '1') then
      Command_Reg <= (others => '0');
    elsif Update'event and Update = '1' then   -- rising clock edge
      if Command_Reg_En = '1' then
        command_Reg <= shift_datain(shift_datain'right-command_Reg'length+1 to shift_datain'right);
      end if;
    end if;
  end process Command_Reg_Handle;

  Command_Reg_DFF : process (Clk) is
    variable prev   : std_logic_vector(command_reg'range);
    variable prev_1 : std_logic_vector(command_reg'range);
  begin  -- process Command_Reg_DFF
    if Clk'event and Clk = '1' then     -- rising clock edge
      if Reset_b then                   -- synchronous reset (active high)
        read_register_MSR <= '0';
        read_register_PC  <= '0';
        prev_1            := (others => '0');
        prev              := (others => '0');
      else
        read_register_MSR <= '0';
        read_register_PC  <= '0';
        if (prev_1(0) = '0' and prev(0) = '1') then
          read_register_MSR <= '1';
        end if;
        if (prev_1(1) = '0' and prev(1) = '1') then
          read_register_PC <= '1';
        end if;
        prev_1 := prev;
        prev   := command_reg;
      end if;
    end if;
  end process Command_Reg_DFF;

  Reg_access_Delay : process (Clk) is
  begin  -- process Reg_access_Delay
    if Clk'event and Clk = '1' then     -- rising clock edge
      if Reset_b then                   -- synchronous reset (active high)
        read_register_PC_1  <= '0';
        read_register_MSR_1 <= '0';
      else
        read_register_PC_1  <= read_register_PC;
        read_register_MSR_1 <= read_register_MSR;
      end if;
    end if;