debug_gti.vhd

Xilinx软核microblaze源码(VHDL)版本7.10

      rest   := temp mod 16;
      temp   := temp / 16;
      str(I) := LUT(rest);
    end loop;  -- I
    return str;
  end function itohex;


  function calc_brks return natural is
    variable t : natural;
  begin  -- function calc_brks
    t := C_NUMBER_OF_PC_BRK + C_NUMBER_OF_WR_ADDR_BRK + C_NUMBER_OF_RD_ADDR_BRK;
    if (C_NUMBER_OF_PC_BRK = 0) then
      t := t + 1;                       -- Need one extra for single stepping
    end if;
    return t;
  end function calc_brks;

  constant C_NR_OF_BRKS : natural := calc_brks;

  signal reset_b : boolean;
  
  signal TDO_Status_Reg  : std_logic;
  signal TDO_Data_Reg    : std_logic;
  signal TDO_Config_Word : std_logic;

  signal Config_Reg_En           : std_logic;
  signal Control_Reg_En          : std_logic;
  signal Status_Reg_En           : std_logic;
  signal Command_Reg_En          : std_logic;
  signal Instr_Insert_Reg_En     : std_logic;
  signal Instr_Insert_Reg_En_1   : std_logic;
  signal Instr_Insert_Reg_En_Clk : std_logic;
  signal Data_Read_Reg_En        : std_logic;

  -----------------------------------------------------------------------------
  -- CPU control signals
  -----------------------------------------------------------------------------

  signal free_running : std_logic;

  signal control_reg : std_logic_vector(0 to 5) := "000000";
  -- Bit 0  Armed
  -- Bit 1  Single Step
  -- Bit 2  Continue from breakpoint
  -- Bit 3  Disable Interrupts
  -- Bit 4  Single_Step_Count bit 0
  -- Bit 5  Single_Step_Count bit 1

  constant single_step_pos_C  : natural := 1;
  constant continue_pos_C     : natural := 2;
  constant dis_intr_pos_C     : natural := 3;
  constant single_value_pos_C : natural := 4;

  signal single_Step_TClk       : std_logic := '0';
  signal continue_from_brk_TClk : std_logic := '0';

  signal start_single_cmd  : std_logic;
  signal start_single_step : std_logic;
  signal continue_from_brk : std_logic;
  signal single_Step_N     : std_logic;
  signal single_Step_CPU   : std_logic;
  signal single_Step_CPU_1 : std_logic;
  signal single_Step_CPU_2 : std_logic;

--  signal single_step_count : natural range 0 to 3;
  signal single_step_count : std_logic_vector(0 to 1);

  signal status_reg : std_logic_vector(0 to 22) := (others => '0');
  -- Bit 0-15 BRK Hit
  -- Bit 16 Stopped
  -- Bit 17 Reset
  -- Bit 18 Instruction after a IMM instruction
  -- Bit 19 Delay_slot instruction
  -- Bit 20 Two instruction backwards was an IMM instruction
  -- Bit 21 MicroBlaze stalled due to FSL
  -- Bit 22 MicroBlaze stalled due to non responsive memory request

  signal fsl_stalled_1    : std_logic;
  signal memory_stalled_1 : std_logic;

  signal Full_32_bit        : std_logic;
  signal Full_32_bit_1      : std_logic;
  signal delay_slot_instr   : std_logic;

  signal Command_Reg_Rst : std_logic;
  signal command_reg     : std_logic_vector(0 to 1) := "00";
  -- Bit 0 Read Register MSR
  -- Bit 1 Read Register PC

  signal read_register_PC    : std_logic;
  signal read_register_PC_1  : std_logic;
  signal read_register_MSR   : std_logic;
  signal read_register_MSR_1 : std_logic;

  signal shift_datain  : std_logic_vector(0 to 31) := (others => '0');

  signal data_read_reg     : std_logic_vector(0 to C_DATA_SIZE) := (others => '0');
  signal data_rd_reg       : std_logic_vector(0 to C_DATA_SIZE);
  signal New_Instr_Reg_TCK : std_logic_vector(0 to C_DATA_SIZE-1) := (others => '0');

  signal New_Dbg_Instr_TCK  : std_logic := '0';
  signal New_Dbg_Instr2_TCK : std_logic := '0';

  signal New_Dbg_Instr_CLK  : std_logic := '0';
  signal New_Dbg_Instr2_CLK : std_logic := '0';

  signal IF_Debug_Ready_i : std_logic;
  signal Start_Dbg_Exec   : std_logic;

  signal ex_dbg_pc_hit_single_step : boolean;
  
  signal dbg_brk             : std_logic;
  signal pc_brk              : std_logic;
  signal watchpoint_brk      : std_logic;
  signal watchpoint_brk_hold : std_logic;
  signal dbg_stop_i          : boolean;

  signal Dbg_Stop_Instr_Fetch_i : std_logic;

  signal WB_Read_Instr : std_logic;
  signal WB_Data_Addr  : std_logic_vector(MEM_Data_Addr'range);

  signal which_pc       : std_logic_vector(0 to C_Nr_of_Brks-1);
  signal armed          : std_logic;
  signal dbg_hit        : std_logic_vector(0 to 15);
  signal dbg_hit_i      : std_logic_vector(0 to C_Nr_of_Brks-1);
  signal dbg_hit_hold_i : std_logic_vector(0 to C_Nr_of_Brks-1);
  signal ex_dbg_hit     : std_logic_vector(0 to C_Nr_of_Brks-1);
  signal mem_dbg_hit    : std_logic_vector(0 to C_Nr_of_Brks-1);
  signal wb_dbg_hit     : std_logic_vector(0 to C_Nr_of_Brks-1);

  signal shift_Count : std_logic_vector(7 downto 0) := (others => '0');

  signal read_pc : std_logic;

  signal Dbg_Inhibit_EX_i : std_logic;

  signal dbg_state_i  : boolean;
  signal dbg_freeze_i : boolean;

begin  -- architecture IMP

  reset_b <= (reset = '1');
  
  -- Keep a counter on the number of bits in the data phase after a sync has
  -- been detected (only needed for BreakPoints and config register)
  Shift_Counter : process (TCLK) is
  begin  -- process Shift_Counter
    if TCLK'event and TCLK = '1' then   -- rising clock edge
      if (Shift = '1') then        
        shift_Count <= std_logic_vector(unsigned(Shift_Count) + 1);
      else
        shift_Count <= (others => '0');
      end if;
    end if;
  end process Shift_Counter;

  Control_Reg_En      <= '1' when Reg_En(0 to 4) = "00001" else '0';
  Command_Reg_En      <= '1' when Reg_En(0 to 4) = "00010" else '0';
  Status_Reg_En       <= '1' when Reg_En(0 to 4) = "00011" else '0';
  Instr_Insert_Reg_En <= '1' when Reg_En(0 to 4) = "00100" else '0';
  Data_Read_Reg_En    <= '1' when Reg_En(0 to 4) = "00110" else '0';
  Config_Reg_En       <= '1' when Reg_En(0 to 4) = "00111" else '0';

  -----------------------------------------------------------------------------
  -- Config Register handling
  -----------------------------------------------------------------------------
  -- pragma xilinx_rtl_off
--  Use_SRL16 : if (C_TARGET /= RTL) generate
  Use_SRL16 : if (TRUE) generate
    signal tdo_config_word1    : std_logic_vector(0 to 13) := (others => '0');
  begin
    SRL16E_1 : SRL16E
      generic map (
        INIT => to_bitvector(Config_Init_Word)
        )
      port map (
        CE  => '0',                     -- [in  std_logic]
        D   => '0',                     -- [in  std_logic]
        Clk => TCLK,                    -- [in  std_logic]
        A0  => shift_Count(0),          -- [in  std_logic]
        A1  => shift_Count(1),          -- [in  std_logic]
        A2  => shift_Count(2),          -- [in  std_logic]
        A3  => shift_Count(3),          -- [in  std_logic]
        Q   => tdo_config_word1(0));    -- [out std_logic]

    SRL16E_2 : SRL16E
      generic map (
        INIT => to_bitvector(Config_Init_Word2)
        )
      port map (
        CE  => '0',                     -- [in  std_logic]
        D   => '0',                     -- [in  std_logic]
        Clk => TCLK,                    -- [in  std_logic]
        A0  => shift_Count(0),          -- [in  std_logic]
        A1  => shift_Count(1),          -- [in  std_logic]
        A2  => shift_Count(2),          -- [in  std_logic]
        A3  => shift_Count(3),          -- [in  std_logic]
        Q   => tdo_config_word1(1));    -- [out std_logic]

    The_Cache_Addresses : for I in 1 to 8 generate
    begin
      SRL16E_Cache_I : SRL16E
        generic map (
          INIT => to_bitvector(Cache_Init_Word(I*16-1 downto (I-1)*16))
          )
        port map (
          CE  => '0',                     -- [in  std_logic]
          D   => '0',                     -- [in  std_logic]
          Clk => TCLK,                    -- [in  std_logic]
          A0  => shift_Count(0),          -- [in  std_logic]
          A1  => shift_Count(1),          -- [in  std_logic]
          A2  => shift_Count(2),          -- [in  std_logic]
          A3  => shift_Count(3),          -- [in  std_logic]
          Q   => tdo_config_word1(1+I));  -- [out std_logic]
    end generate The_Cache_Addresses;

    -- placed after cache information for compatibility with 8.1 tools
    SRL16E_3 : SRL16E
      generic map (
        INIT => to_bitvector(Config_Init_Word3)
        )
      port map (
        CE  => '0',                     -- [in  std_logic]
        D   => '0',                     -- [in  std_logic]
        Clk => TCLK,                    -- [in  std_logic]
        A0  => shift_Count(0),          -- [in  std_logic]
        A1  => shift_Count(1),          -- [in  std_logic]
        A2  => shift_Count(2),          -- [in  std_logic]
        A3  => shift_Count(3),          -- [in  std_logic]
        Q   => tdo_config_word1(10));   -- [out std_logic]

    -- PVR0 register information
    SRL16E_4 : SRL16E
      generic map (
        INIT => to_bitvector(Config_Init_Word4)
        )
      port map (
        CE  => '0',                     -- [in  std_logic]
        D   => '0',                     -- [in  std_logic]
        Clk => TCLK,                    -- [in  std_logic]
        A0  => shift_Count(0),          -- [in  std_logic]
        A1  => shift_Count(1),          -- [in  std_logic]
        A2  => shift_Count(2),          -- [in  std_logic]
        A3  => shift_Count(3),          -- [in  std_logic]
        Q   => tdo_config_word1(11));   -- [out std_logic]

    -- PVR1 register information
    Use_PVR_Full: if C_PVR = 2 generate
      -- High USER2 half-word
      SRL16E_5 : SRL16E
        generic map (
          INIT => to_bitvector(Config_Init_Word5)
          )
        port map (
          CE  => '0',                     -- [in  std_logic]
          D   => '0',                     -- [in  std_logic]
          Clk => TCLK,                    -- [in  std_logic]
          A0  => shift_Count(0),          -- [in  std_logic]
          A1  => shift_Count(1),          -- [in  std_logic]
          A2  => shift_Count(2),          -- [in  std_logic]
          A3  => shift_Count(3),          -- [in  std_logic]
          Q   => tdo_config_word1(12));   -- [out std_logic]
      -- Low USER2 half-word
      SRL16E_6 : SRL16E
        generic map (
          INIT => to_bitvector(Config_Init_Word6)
          )
        port map (
          CE  => '0',                     -- [in  std_logic]
          D   => '0',                     -- [in  std_logic]
          Clk => TCLK,                    -- [in  std_logic]
          A0  => shift_Count(0),          -- [in  std_logic]
          A1  => shift_Count(1),          -- [in  std_logic]
          A2  => shift_Count(2),          -- [in  std_logic]
          A3  => shift_Count(3),          -- [in  std_logic]
          Q   => tdo_config_word1(13));   -- [out std_logic]
    end generate Use_PVR_Full;

    SRL16_Mux : process (shift_Count, tdo_config_word1) is
    begin  -- process SRL16_Mux
      case shift_Count(7 downto 4) is
        when "0000" => TDO_Config_Word <= tdo_config_word1(0);
        when "0001" => TDO_Config_Word <= tdo_config_word1(1);
        when "0010" => TDO_Config_Word <= tdo_config_word1(2);
        when "0011" => TDO_Config_Word <= tdo_config_word1(3);
        when "0100" => TDO_Config_Word <= tdo_config_word1(4);
        when "0101" => TDO_Config_Word <= tdo_config_word1(5);
        when "0110" => TDO_Config_Word <= tdo_config_word1(6);
        when "0111" => TDO_Config_Word <= tdo_config_word1(7);
        when "1000" => TDO_Config_Word <= tdo_config_word1(8);
        when "1001" => TDO_Config_Word <= tdo_config_word1(9);
        when "1010" => TDO_Config_Word <= tdo_config_word1(10);
        when "1011" => TDO_Config_Word <= tdo_config_word1(11);
        when "1100" => TDO_Config_Word <= tdo_config_word1(12);
        when "1101" => TDO_Config_Word <= tdo_config_word1(13);
        when others => TDO_Config_Word <= tdo_config_word1(0);
      end case;
    end process SRL16_Mux;
  end generate Use_SRL16;
  -- pragma xilinx_rtl_on

  -- pragma xilinx_fpga_off
  -- pragma xilinx_rtl_off
--  Not_Use_SRL16 : if (C_TARGET = RTL) generate
--    -- pragma xilinx_rtl_on
--    Config_TDO_Selecting : process (shift_Count) is
--    begin  -- process Config_TDO_Selecting
--      if (shift_Count(7 downto 4) = "0000") then
--        TDO_Config_Word <= Config_Init_Word(to_integer(unsigned(shift_Count(3 downto 0))));
--      elsif (shift_Count(7 downto 4) = "0001") then
--        TDO_Config_Word <= Config_Init_Word2(to_integer(unsigned(shift_Count(3 downto 0))));
--      else
--        TDO_Config_Word <= Cache_Init_Word(to_integer((unsigned(shift_Count) - 32)) mod Cache_Init_Word'length);
--      end if;
--    end process Config_TDO_Selecting;
--    -- pragma xilinx_rtl_off
--  end generate Not_Use_SRL16;
  -- pragma xilinx_rtl_on
  -- pragma xilinx_fpga_on

  -----------------------------------------------------------------------------
  -- Handling Status Register
  -----------------------------------------------------------------------------

  Using_full_32_bit_immediates : process (Clk) is
  begin  -- process Using_full_32_bit_immediates
    if Clk'event and Clk = '1' then     -- rising clock edge
      if Reset_b then                     -- synchronous reset (active true)
        Full_32_bit   <= '0';
        Full_32_bit_1 <= '0';
      elsif WB_Halted then
        if (WB_Read_Imm_Reg) then
          Full_32_bit <= '1';
        else
          Full_32_bit <= '0';
        end if;
        if (WB_Read_Imm_Reg_1) then
          Full_32_bit_1 <= '1';
        else
          Full_32_bit_1 <= '0';
        end if;