interrupt_mode_converter.vhd

Xilinx软核microblaze源码(VHDL)版本7.10

--SINGLE_FILE_TAG
-------------------------------------------------------------------------------
-- $Id: interrupt_mode_converter.vhd,v 1.1 2007/10/12 09:11:36 stefana Exp $
-------------------------------------------------------------------------------
-- MicroBlaze - entity/architecture
-------------------------------------------------------------------------------
--
--                  ****************************
--                  ** Copyright Xilinx, Inc. **
--                  ** All rights reserved.   **
--                  ****************************
--
-------------------------------------------------------------------------------
-- Filename:        interrupt_mode_converter.vhd
-- Version:         v1.00a
-- Description:     Converts incomming interrupt mode to fixed internal
--                  MicroBlaze standard based on user generics
--                  
-------------------------------------------------------------------------------
-- Structure:   
--
-------------------------------------------------------------------------------
-- Author:  
-- History:
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- Naming Conventions:
--      active low signals:                     "*_n"
--      clock signals:                          "clk", "*_clk"
--      reset signals:                          "rst", "*_rst", "reset"
--      generics:                               All uppercase, starting with: "C_"
--      constants:                              All uppercase, not starting with: "C_"
--      state machine next state:               "*_next_state"
--      state machine current state:            "*_curr_state"
--      pipelined signals:                      "*_d#"
--      counter signals:                        "*_cnt_*" , "*_counter_*", "*_count_*"
--      internal version of output port:        "*_i"
--      ports:                                  Names begin with uppercase
--      component instantiations:               "<ENTITY>_I#|<FUNC>" , "<ENTITY>_I"
-------------------------------------------------------------------------------

library IEEE;
use IEEE.std_logic_1164.all;

library Microblaze_v7_10_a;
use Microblaze_v7_10_a.MicroBlaze_ISA.all;
use Microblaze_v7_10_a.MicroBlaze_Types.all;

entity interrupt_mode_converter is
  
  generic (
    C_INTERRUPT_IS_EDGE : boolean := false;
    C_EDGE_IS_POSITIVE  : boolean := false);

  port (
    Clk                : in  std_logic;
    External_interrupt : in  std_logic;
    Interrupt_taken    : in  std_logic;
    Internal_interrupt : out rboolean);

end interrupt_mode_converter;

architecture IMP of interrupt_mode_converter is

begin  -- IMP
  
  Interrupt_Is_Level_High : if (not C_INTERRUPT_IS_EDGE) generate
    Internal_interrupt <= (External_interrupt = '1');
  end generate Interrupt_Is_Level_High;

  Interrupt_Is_Edge_Positive : if (C_INTERRUPT_IS_EDGE and C_EDGE_IS_POSITIVE) generate
    Pos_Edge_Detection : process (Clk) is
      variable external_interrupt_d1 : std_logic := '0';
    begin  -- process Pos_Edge_Detection
      if Clk'event and Clk = '1' then   -- rising clock edge
        if ((not external_interrupt_d1 and External_interrupt) = '1') then
          Internal_Interrupt <= true;
        elsif (Interrupt_taken = '1') then
          Internal_interrupt <= false;
        end if;
        external_interrupt_d1 := External_interrupt;
      end if;
    end process Pos_Edge_Detection;
  end generate Interrupt_Is_Edge_Positive;

  Interrupt_Is_Edge_Negative : if (C_INTERRUPT_IS_EDGE and not C_EDGE_IS_POSITIVE) generate
    Neg_Edge_Detection : process (Clk) is
      variable external_interrupt_d1 : std_logic := '0';
    begin  -- process Neg_Edge_Detection
      if Clk'event and Clk = '1' then   -- rising clock edge
        if ((external_interrupt_d1 and not External_interrupt) = '1') then
          Internal_interrupt <= true;
        elsif (Interrupt_taken = '1') then
          Internal_interrupt <= false;
        end if;
        external_interrupt_d1 := External_interrupt;
      end if;
    end process Neg_Edge_Detection;
  end generate Interrupt_Is_Edge_Negative;

end IMP;