register_file_bit.vhd

Xilinx软核microblaze源码(VHDL)版本7.10

--SINGLE_FILE_TAG
-------------------------------------------------------------------------------
-- $Id: register_file_bit.vhd,v 1.1 2007/10/12 09:11:36 stefana Exp $
-------------------------------------------------------------------------------
-- Register_File_Bit - entity/architecture
-------------------------------------------------------------------------------
--
--                  ****************************
--                  ** Copyright Xilinx, Inc. **
--                  ** All rights reserved.   **
--                  ****************************
--
-------------------------------------------------------------------------------
-- Filename:        register_file_bit.vhd
-- Version:         v1.00a
-- Description:     Implements 1 bit of the register file
--                  
-------------------------------------------------------------------------------
-- Structure:   
--              register_file_bit.vhd
--
-------------------------------------------------------------------------------
-- Author:          goran
-- History:
--   goran  2001-03-05    First Version
--
-------------------------------------------------------------------------------
-- Naming Conventions:
--      active low signals:                     "*_n"
--      clock signals:                          "clk", "clk_div#", "clk_#x" 
--      reset signals:                          "rst", "rst_n" 
--      generics:                               "C_*" 
--      user defined types:                     "*_TYPE" 
--      state machine next state:               "*_ns" 
--      state machine current state:            "*_cs" 
--      combinatorial signals:                  "*_com" 
--      pipelined or register delay signals:    "*_d#" 
--      counter signals:                        "*cnt*"
--      clock enable signals:                   "*_ce" 
--      internal version of output port         "*_i"
--      device pins:                            "*_pin" 
--      ports:                                  - Names begin with Uppercase 
--      processes:                              "*_PROCESS" 
--      component instantiations:               "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------

library IEEE;
use IEEE.std_logic_1164.all;
library Microblaze_v7_10_a;
use Microblaze_v7_10_a.MicroBlaze_Types.all;


-------------------------------------------------------------------------------
-- Port declarations
-------------------------------------------------------------------------------

entity Register_File_Bit is

  generic (
    C_TARGET : TARGET_FAMILY_TYPE);
  port (
    Clk        : in  std_logic;
    Write_Addr : in  std_logic_vector(0 to 4);
    Reg1_Addr  : in  std_logic_vector(0 to 4);
    Reg2_Addr  : in  std_logic_vector(0 to 4);
    Reg_Write  : in  boolean;
    EX_Result  : in  std_logic;
    Data_Write : out std_logic;
    Reg1_Data  : out std_logic;
    Reg2_Data  : out std_logic
    );

end entity Register_File_Bit;

-------------------------------------------------------------------------------
-- Architecture section
-------------------------------------------------------------------------------

library Unisim;
use Unisim.vcomponents.all;

architecture IMP of Register_File_Bit is
-------------------------------------------------------------------------------
-- Begin architecture
-------------------------------------------------------------------------------
  
begin  -- IMP

  Using_Virtex2 : if (C_TARGET = VIRTEX2) or (C_TARGET = VIRTEX2PRO) or (C_TARGET = VIRTEX5) generate
    signal reg_WE          : std_logic;
  begin
    reg_WE <= '1' when Reg_Write else '0';

    RegFile_X1 : RAM32x1D
      port map (
        WE    => reg_WE,
        D     => EX_Result,
        WClk  => Clk,
        A0    => Write_Addr(0),
        A1    => Write_Addr(1),
        A2    => Write_Addr(2),
        A3    => Write_Addr(3),
        A4    => Write_Addr(4),
        DPRA0 => Reg1_Addr(0),
        DPRA1 => Reg1_Addr(1),
        DPRA2 => Reg1_Addr(2),
        DPRA3 => Reg1_Addr(3),
        DPRA4 => Reg1_Addr(4),
        SPO   => Data_Write,
        DPO   => Reg1_Data
        );

    RegFile_X2 : RAM32x1D
      port map (
        WE    => Reg_WE,
        D     => EX_Result,
        WClk  => Clk,
        A0    => Write_Addr(0),
        A1    => Write_Addr(1),
        A2    => Write_Addr(2),
        A3    => Write_Addr(3),
        A4    => Write_Addr(4),
        DPRA0 => Reg2_Addr(0),
        DPRA1 => Reg2_Addr(1),
        DPRA2 => Reg2_Addr(2),
        DPRA3 => Reg2_Addr(3),
        DPRA4 => Reg2_Addr(4),
        SPO   => open,
        DPO   => Reg2_Data
        );
  end generate Using_Virtex2;

  Using_Virtex : if (C_TARGET = VIRTEX) or (C_TARGET = VIRTEXE) or
                    (C_TARGET = SPARTANII) or (C_TARGET = SPARTANIIE) generate

    signal reg_WE_Low      : std_logic;
    signal reg_WE_High     : std_logic;
    signal data_Write_Low  : std_logic;
    signal data_Write_High : std_logic;
    signal reg1_Data_Low   : std_logic;
    signal reg1_Data_High  : std_logic;
    signal reg2_Data_Low   : std_logic;
    signal reg2_Data_High  : std_logic;

  begin
    reg_WE_Low  <= '1' when Reg_Write and (Write_Addr(4) = '0') else '0';
    reg_WE_High <= '1' when Reg_Write and (Write_Addr(4) = '1') else '0';

    RAM16x1D_Reg1_Low : RAM16x1D
      port map (
        WE    => reg_WE_Low,            -- [in  std_logic]
        D     => EX_Result,             -- [in  std_logic]
        WClk  => Clk,                   -- [in  std_logic]
        A0    => Write_Addr(0),         -- [in  std_logic]
        A1    => Write_Addr(1),         -- [in  std_logic]
        A2    => Write_Addr(2),         -- [in  std_logic]
        A3    => Write_Addr(3),         -- [in  std_logic]
        DPRA0 => Reg1_Addr(0),          -- [in  std_logic]
        DPRA1 => Reg1_Addr(1),          -- [in  std_logic]
        DPRA2 => Reg1_Addr(2),          -- [in  std_logic]
        DPRA3 => Reg1_Addr(3),          -- [in  std_logic]
        SPO   => data_Write_Low,        -- [out std_logic]
        DPO   => reg1_Data_Low);        -- [out std_logic]


    RAM16x1D_Reg1_High : RAM16x1D
      port map (
        WE    => reg_WE_High,           -- [in  std_logic]
        D     => EX_Result,             -- [in  std_logic]
        WClk  => Clk,                   -- [in  std_logic]
        A0    => Write_Addr(0),         -- [in  std_logic]
        A1    => Write_Addr(1),         -- [in  std_logic]
        A2    => Write_Addr(2),         -- [in  std_logic]
        A3    => Write_Addr(3),         -- [in  std_logic]
        DPRA0 => Reg1_Addr(0),          -- [in  std_logic]
        DPRA1 => Reg1_Addr(1),          -- [in  std_logic]
        DPRA2 => Reg1_Addr(2),          -- [in  std_logic]
        DPRA3 => Reg1_Addr(3),          -- [in  std_logic]
        SPO   => data_Write_High,       -- [out std_logic]
        DPO   => reg1_Data_High);       -- [out std_logic]

    Data_Write_Mux : LUT3
      generic map (
        INIT => X"CA")                  -- [bit_vector]
      port map (
        O  => Data_Write,               -- [out std_logic]
        I0 => data_Write_Low,           -- [in  std_logic]
        I1 => data_Write_High,          -- [in  std_logic]
        I2 => Write_Addr(4));           -- [in std_logic]

    Reg1_Mux : LUT3
      generic map (
        INIT => X"CA")                  -- [bit_vector]
      port map (
        O  => Reg1_Data,                -- [out std_logic]
        I0 => reg1_Data_Low,            -- [in  std_logic]
        I1 => reg1_Data_High,           -- [in  std_logic]
        I2 => Reg1_Addr(4));            -- [in std_logic]

    RAM16x1D_Reg2_Low : RAM16x1D
      port map (
        WE    => reg_WE_Low,            -- [in  std_logic]
        D     => EX_Result,             -- [in  std_logic]
        WClk  => Clk,                   -- [in  std_logic]
        A0    => Write_Addr(0),         -- [in  std_logic]
        A1    => Write_Addr(1),         -- [in  std_logic]
        A2    => Write_Addr(2),         -- [in  std_logic]
        A3    => Write_Addr(3),         -- [in  std_logic]
        DPRA0 => Reg2_Addr(0),          -- [in  std_logic]
        DPRA1 => Reg2_Addr(1),          -- [in  std_logic]
        DPRA2 => Reg2_Addr(2),          -- [in  std_logic]
        DPRA3 => Reg2_Addr(3),          -- [in  std_logic]
        SPO   => open,                  -- [out std_logic]
        DPO   => reg2_Data_Low);        -- [out std_logic]


    RAM16x1D_Reg2_High : RAM16x1D
      port map (
        WE    => reg_WE_High,           -- [in  std_logic]
        D     => EX_Result,             -- [in  std_logic]
        WClk  => Clk,                   -- [in  std_logic]
        A0    => Write_Addr(0),         -- [in  std_logic]
        A1    => Write_Addr(1),         -- [in  std_logic]
        A2    => Write_Addr(2),         -- [in  std_logic]
        A3    => Write_Addr(3),         -- [in  std_logic]
        DPRA0 => Reg2_Addr(0),          -- [in  std_logic]
        DPRA1 => Reg2_Addr(1),          -- [in  std_logic]
        DPRA2 => Reg2_Addr(2),          -- [in  std_logic]
        DPRA3 => Reg2_Addr(3),          -- [in  std_logic]
        SPO   => open,                  -- [out std_logic]
        DPO   => reg2_Data_High);       -- [out std_logic]

    Reg2_Mux : LUT3
      generic map (
        INIT => X"CA")                  -- [bit_vector]
      port map (
        O  => Reg2_Data,                -- [out std_logic]
        I0 => reg2_Data_Low,            -- [in  std_logic]
        I1 => reg2_Data_High,           -- [in  std_logic]
        I2 => Reg2_Addr(4));            -- [in std_logic]

  end generate Using_Virtex;

  Using_Virtex4_and_S3 : if (C_TARGET = VIRTEX4)    or (C_TARGET = SPARTAN3)     or
                            (C_TARGET = SPARTAN3A)  or (C_TARGET = SPARTAN3E)    or
                            (C_TARGET = SPARTAN3AN) or (C_TARGET = SPARTAN3Adsp) generate

    signal reg_WE_Low      : std_logic;
    signal reg_WE_High     : std_logic;
    signal data_Write_Low  : std_logic;
    signal data_Write_High : std_logic;
    signal reg1_Data_Low   : std_logic;
    signal reg1_Data_High  : std_logic;
    signal reg2_Data_Low   : std_logic;
    signal reg2_Data_High  : std_logic;
  begin
    reg_WE_Low  <= '1' when Reg_Write and (Write_Addr(4) = '0') else '0';
    reg_WE_High <= '1' when Reg_Write and (Write_Addr(4) = '1') else '0';

    RAM16x1D_Reg1_Low : RAM16x1D
      port map (
        WE    => reg_WE_Low,            -- [in  std_logic]
        D     => EX_Result,             -- [in  std_logic]
        WClk  => Clk,                   -- [in  std_logic]
        A0    => Write_Addr(0),         -- [in  std_logic]
        A1    => Write_Addr(1),         -- [in  std_logic]
        A2    => Write_Addr(2),         -- [in  std_logic]
        A3    => Write_Addr(3),         -- [in  std_logic]
        DPRA0 => Reg1_Addr(0),          -- [in  std_logic]
        DPRA1 => Reg1_Addr(1),          -- [in  std_logic]
        DPRA2 => Reg1_Addr(2),          -- [in  std_logic]
        DPRA3 => Reg1_Addr(3),          -- [in  std_logic]
        SPO   => data_Write_Low,        -- [out std_logic]
        DPO   => reg1_Data_Low);        -- [out std_logic]


    RAM16x1D_Reg1_High : RAM16x1D
      port map (
        WE    => reg_WE_High,           -- [in  std_logic]
        D     => EX_Result,             -- [in  std_logic]
        WClk  => Clk,                   -- [in  std_logic]
        A0    => Write_Addr(0),         -- [in  std_logic]
        A1    => Write_Addr(1),         -- [in  std_logic]
        A2    => Write_Addr(2),         -- [in  std_logic]
        A3    => Write_Addr(3),         -- [in  std_logic]
        DPRA0 => Reg1_Addr(0),          -- [in  std_logic]
        DPRA1 => Reg1_Addr(1),          -- [in  std_logic]
        DPRA2 => Reg1_Addr(2),          -- [in  std_logic]
        DPRA3 => Reg1_Addr(3),          -- [in  std_logic]
        SPO   => data_Write_High,       -- [out std_logic]
        DPO   => reg1_Data_High);       -- [out std_logic]

    Data_Write_Mux : LUT3
      generic map (
        INIT => X"CA")                  -- [bit_vector]
      port map (
        O  => Data_Write,               -- [out std_logic]
        I0 => data_Write_Low,           -- [in  std_logic]
        I1 => data_Write_High,          -- [in  std_logic]
        I2 => Write_Addr(4));           -- [in std_logic]

    Reg1_Mux : LUT3
      generic map (
        INIT => X"CA")                  -- [bit_vector]
      port map (
        O  => Reg1_Data,                -- [out std_logic]
        I0 => reg1_Data_Low,            -- [in  std_logic]
        I1 => reg1_Data_High,           -- [in  std_logic]
        I2 => Reg1_Addr(4));            -- [in std_logic]

    RAM16x1D_Reg2_Low : RAM16x1D
      port map (
        WE    => reg_WE_Low,            -- [in  std_logic]
        D     => EX_Result,             -- [in  std_logic]
        WClk  => Clk,                   -- [in  std_logic]
        A0    => Write_Addr(0),         -- [in  std_logic]
        A1    => Write_Addr(1),         -- [in  std_logic]
        A2    => Write_Addr(2),         -- [in  std_logic]
        A3    => Write_Addr(3),         -- [in  std_logic]
        DPRA0 => Reg2_Addr(0),          -- [in  std_logic]
        DPRA1 => Reg2_Addr(1),          -- [in  std_logic]
        DPRA2 => Reg2_Addr(2),          -- [in  std_logic]
        DPRA3 => Reg2_Addr(3),          -- [in  std_logic]
        SPO   => open,                  -- [out std_logic]
        DPO   => reg2_Data_Low);        -- [out std_logic]


    RAM16x1D_Reg2_High : RAM16x1D
      port map (
        WE    => reg_WE_High,           -- [in  std_logic]
        D     => EX_Result,             -- [in  std_logic]
        WClk  => Clk,                   -- [in  std_logic]
        A0    => Write_Addr(0),         -- [in  std_logic]
        A1    => Write_Addr(1),         -- [in  std_logic]
        A2    => Write_Addr(2),         -- [in  std_logic]
        A3    => Write_Addr(3),         -- [in  std_logic]
        DPRA0 => Reg2_Addr(0),          -- [in  std_logic]
        DPRA1 => Reg2_Addr(1),          -- [in  std_logic]
        DPRA2 => Reg2_Addr(2),          -- [in  std_logic]
        DPRA3 => Reg2_Addr(3),          -- [in  std_logic]
        SPO   => open,                  -- [out std_logic]
        DPO   => reg2_Data_High);       -- [out std_logic]

    Reg2_Mux : LUT3
      generic map (
        INIT => X"CA")                  -- [bit_vector]
      port map (
        O  => Reg2_Data,                -- [out std_logic]
        I0 => reg2_Data_Low,            -- [in  std_logic]
        I1 => reg2_Data_High,           -- [in  std_logic]
        I2 => Reg2_Addr(4));            -- [in std_logic]

  end generate Using_Virtex4_and_S3;

end architecture IMP;