fpu.vhd

Xilinx软核microblaze源码(VHDL)版本7.10

  
    signal ex_SignB_1 : std_logic;
    signal ex_ExpB_1  : FPU_EXP_TYPE;
    signal ex_MantB_1 : FPU_MANT_TYPE;
  
    -- Stage 2
    signal ex_MantA_Zero_2_cmb   : boolean;
    signal ex_MantA_Zero_2_cmb_s : std_logic;
    signal ex_MantB_Zero_2_cmb   : boolean;
    signal ex_MantB_Zero_2_cmb_s : std_logic;
    signal ex_ExpA_Zero_2_cmb    : boolean;
    signal ex_ExpB_Zero_2_cmb    : boolean;
    signal ex_ExpA_Ones_2_cmb    : boolean;
    signal ex_ExpB_Ones_2_cmb    : boolean;
    signal ex_Exp_AsubB_2_i      : Exp_Plus2_T;
    signal ex_Exp_AsubB_2_cmb    : FPU_EXP_TYPE;

    signal ex_Exp_BgtA_2_cmb       : boolean;
    signal ex_Exp_Equal_2_cmb      : boolean;
    signal ex_Exp_Equal_2_cmb_s    : std_logic;
    signal ex_Exp_absAsubB_2_cmb_i : Exp_Plus2_T;
    signal ex_Exp_absAsubB_2_cmb   : FPU_EXP_TYPE;
  
    -- signal ex_Mant_AsubB_2_cmb : FPU_MANT_I_TYPE;
    signal ex_Mant_BgtA_2_cmb        : boolean;
    signal ex_Exp_Mant_Equal_2_cmb   : boolean;
    signal ex_Exp_Mant_Equal_2_cmb_s : std_logic;
  
    signal ex_absBgtA_2_cmb    : boolean;
    signal ex_A_Zero_2_cmb     : boolean;
    signal ex_B_Zero_2_cmb     : boolean;
    signal ex_A_NaN_2_cmb      : boolean;
    signal ex_B_NaN_2_cmb      : boolean;

    signal mem_float_operation_2 : boolean;
    signal mem_add_op_2          : boolean;
    signal mem_sub_op_2          : boolean;
    signal mem_cmp_op_2          : boolean;
    signal mem_cmp_cond_2        : FPU_COND_TYPE;
    signal mem_mul_op_2          : boolean;
    signal mem_div_op_2          : boolean;
    signal mem_sqrt_op_2         : boolean;
    signal mem_flt_op_2          : boolean;
    signal mem_int_op_2          : boolean;

    signal mem_addsub_sel_2 : std_logic;
  
    signal mem_SignA_2 : std_logic;
    signal mem_SignB_2 : std_logic;
  
    signal mem_MantA_2 : FPU_MANT_I_TYPE;
    signal mem_MantB_2 : FPU_MANT_I_TYPE;
  
    signal mem_Exp_absAsubB_2 : FPU_EXP_TYPE;
  
    -- input types
    signal mem_NanA_2    : boolean;
    signal mem_NanB_2    : boolean;
    signal mem_QNanA_2   : boolean;
    signal mem_QNanB_2   : boolean;
    signal mem_SNanA_2   : boolean;
    signal mem_SNanB_2   : boolean;
    signal mem_DeNormA_2 : boolean;
    signal mem_DeNormB_2 : boolean;
    signal mem_InfA_2    : boolean;
    signal mem_InfB_2    : boolean;
    signal mem_ZeroA_2   : boolean;
    signal mem_ZeroB_2   : boolean;
  
    signal mem_absAgtB_2   : boolean;
    signal mem_Exp_Res_2   : Exp_Plus2_T;
    signal mem_add_mant_2  : boolean;
    signal mem_Res_Sign_2  : std_logic;
  
    -- Comparisons
    signal mem_cmp_eq_2    : boolean;
    signal mem_cmp_lt_2    : boolean;
    signal mem_cmp_gt_2    : boolean;
    signal mem_cmp_un_2    : boolean;
  
    -- Stage 3
    signal mem_mul_op_3         : boolean;
    signal mem_div_op_3         : boolean;
    signal mem_sqrt_op_3        : boolean;
    signal mem_flt_op_3        : boolean;
    signal mem_int_op_3        : boolean;
    signal mem_addsub_op_3      : boolean;
    signal mem_Exp_AddSub_3_cmb : Exp_Plus2_T;
    signal mem_Exp_Res_3        : Exp_Plus2_T;
    signal mem_Res_Sign_3       : std_logic;
    signal mem_Normal_Res_3     : boolean;
    signal mem_Res_Type_3       : Result_T;

    -- Stage 4 
    signal mem_mul_op_4           : boolean;
    signal mem_div_op_4           : boolean;
    signal mem_sqrt_op_4          : boolean;
    signal mem_flt_op_4           : boolean;
    signal mem_int_op_4           : boolean;
    signal mem_addsub_zero_4      : boolean;
    signal mem_addsub_op_4        : boolean;
    signal mem_addsub_inc_exp_4   : boolean;
    signal mem_addsub_sub_exp_4   : FPU_EXP_LS_TYPE;
    signal mem_Normal_Res_4       : boolean;
    signal mem_Res_Type_4         : Result_T;
    signal mem_Exp_Res_4          : Exp_Plus2_T;
    signal mem_Res_Sign_4         : std_logic;
    signal mem_mant_div_res_4     : FPU_MANT_IGRS_TYPE;
    signal mem_div_dec_exp_4      : boolean;

    signal mem_sqrt_done     : rboolean;
    signal mem_sqrt_exp_4    : FPU_EXP_TYPE;      
    signal mem_sqrt_result_4 : FPU_MANT_IGRS_TYPE;

    signal mem_flt_done       : rboolean;
    signal mem_flt_result_4   : FPU_MANT_IGRS_TYPE;
    signal mem_flt_exp_4      : FPU_EXP_TYPE;
    signal mem_int_done       : rboolean;
    signal mem_int_done_early : rboolean;
    signal mem_int_zero_3     : rboolean;
    signal mem_int_inv_3      : rboolean;
    signal mem_int_result_5   : DATA_TYPE;
    
    -- Stage 5
    signal mem_addsub_zero_5         : boolean;

    signal mem_inc_exp_5_cmb         : boolean;
    signal mem_mant_res_5_cmb        : FPU_MANT_IGRS_TYPE;
    signal mem_mant_ls16_5_cmb       : std_logic;
    signal mem_mant_addsub_res_5_cmb : FPU_MANT_IGRS_TYPE;
    signal mem_mant_mul_res_5_cmb    : FPU_MANT_IGRS_TYPE;
    signal mem_mul_inc_exp_5_cmb     : boolean;
    signal mem_Exp_Res_5_cmb         : Exp_Plus2_T;

    signal mem_exp_borrow_5_cmb      : boolean;
    signal mem_exp_overflow_5_cmb    : boolean;
    signal mem_exp_zero_5_cmb        : boolean;
    signal mem_exp_ones_5_cmb        : boolean;

    signal mem_round_up_5            : boolean;
    signal mem_Normal_Res_5          : boolean;
    signal mem_Res_Type_5            : Result_T;
    signal mem_Res_Sign_5            : std_logic;
    signal mem_Exp_Res_5             : Exp_Plus2_T;
    signal mem_mant_res_5            : FPU_MANT_TYPE;
    signal mem_mant_res_5_ones       : boolean;
    signal mem_inc_exp_5             : boolean;
  
    -- Stage 6

    signal mem_cmp_op_6_cmb   : boolean;
    signal mem_cmp_cond_6_cmb : FPU_COND_TYPE;

    signal mem_cond_gt_6_cmb  : boolean;
    signal mem_cond_eq_6_cmb  : boolean;
    signal mem_cond_lt_6_cmb  : boolean;
    signal mem_cond_un_6_cmb  : boolean;

    signal mem_inc_exp_6_cmb           : boolean;
    signal mem_mant_res_6_cmb          : FPU_MANT_TYPE;
    signal mem_exp_res_6_cmb           : Exp_Plus2_T;
    signal mem_exp_over_6_cmb          : boolean;
    signal mem_rounding_overflow_6_cmb : boolean;

    signal mem_res_sign_rst_6_cmb     : boolean;
    signal mem_res_sign_set_6_cmb     : boolean;
    signal mem_res_exp_rst_6_cmb      : boolean;
    signal mem_res_exp_set_6_cmb      : boolean;
    signal mem_res_mant_rst_msb_6_cmb : boolean;
    signal mem_res_mant_rst_mid_6_cmb : boolean;
    signal mem_res_mant_rst_lsb_6_cmb : boolean;
    signal mem_res_mant_set_msb_6_cmb : boolean;
    signal mem_res_mant_set_mid_6_cmb : boolean;
    signal mem_res_mant_set_lsb_6_cmb : boolean;

    signal mem_FPU_Flags_6_cmb        : FSR_TYPE;
  
    -- FSR
    signal mem_mts_fsr  : std_logic;
    signal mem_op1      : FSR_TYPE;
    signal mem_fsr_cmb  : FSR_TYPE;
    signal wb_fsr_i     : FSR_TYPE;

    
    signal mem_fpu_cmp_done   : boolean;
    signal mem_fpu_div_done   : boolean;
    signal mem_fpu_norm_delay : std_logic_vector(0 to 3);
    signal mem_fpu_done_i     : rboolean;  -- FPU is done the next cycle
    signal mem_fpu_stall_i    : rboolean;  -- FPU is stalling Mem Stage
    signal mem_fpu_excep_i    : rboolean;
    signal wb_fpu_excep_i     : rboolean;

    signal mem_fpu_excep_early : rboolean;
    signal mem_fpu_done_early  : rboolean;
    signal mem_fpu_done_delay  : rboolean;

    signal Block_FPU : boolean;

    signal mem_not_sqrt_op : boolean;
    signal mem_not_div_op  : boolean;

  begin

    ---------------------------------------------------------------------------
    ---------------------------------------------------------------------------
    -- 
    --  Handling the control of the Pipeline
    -- 
    ---------------------------------------------------------------------------
    ---------------------------------------------------------------------------
    ----------------------------------------------    signal ex_sqrt_op : boolean;
-------------------------------
    -- EX Stage
    -----------------------------------------------------------------------------

    mem_not_sqrt_op <= MEM_Not_FPU_Instr or not(mem_sqrt_op_2);
    mem_not_div_op  <= MEM_Not_FPU_Instr or not(mem_div_op_2);
    
    Block_FPU <= true;
    
    -- Decode the operation to perform
    ex_add_op  <= Block_FPU and (EX_FPU_Op = FPU_OP_ADD_DEC);
    ex_sub_op  <= Block_FPU and (EX_FPU_Op = FPU_OP_SUB_DEC);
    ex_mul_op  <= Block_FPU and (EX_FPU_Op = FPU_OP_MUL_DEC);
    ex_div_op  <= Block_FPU and (EX_FPU_Op = FPU_OP_DIV_DEC);
    ex_cmp_op  <= Block_FPU and (EX_FPU_Op = FPU_OP_CMP_DEC);
    ex_flt_op  <= Block_FPU and (EX_FPU_Op = FPU_OP_FLT_DEC) and (C_USE_FPU > 1);
    ex_int_op  <= Block_FPU and (EX_FPU_Op = FPU_OP_INT_DEC) and (C_USE_FPU > 1);
    ex_sqrt_op <= Block_FPU and (EX_FPU_Op = FPU_OP_SQRT_DEC) and (C_USE_FPU > 1);
  
    
    -----------------------------------------------------------------------------
    -- MEM_FPU_Norm_Delay_SRL16
    -- Indicates the end of a FPU add/sub/mul operation
    -----------------------------------------------------------------------------
    MEM_FPU_Norm_Delay_SRL16 : process (Clk) is
    begin -- process MEM_FPU_Norm_Delay_SRL16
      if Clk'event and Clk = '1' then  -- rising clock edge
        if (EX_PipeRun and EX_Start_FPU and not ex_div_op and not ex_cmp_op and not ex_sqrt_op and not ex_flt_op) then
          mem_fpu_norm_delay(0) <= '1';
        else
          mem_fpu_norm_delay(0) <= '0';
        end if;

        -- Shift right
        mem_fpu_norm_delay(1 to mem_fpu_norm_delay'right) <=
          mem_fpu_norm_delay(0 to mem_fpu_norm_delay'right-1);
      end if;
    end process MEM_FPU_Norm_Delay_SRL16;

    -----------------------------------------------------------------------------
    -- MEM_FPU_Cmp_Done_DFF
    -- FPU Compare Instruction is done
    -----------------------------------------------------------------------------
    MEM_FPU_Cmp_Done_DFF : process (Clk) is
    begin -- process MEM_FPU_Cmp_Done_DFF
      if Clk'event and Clk = '1' then  -- rising clock edge
        if Reset = '1' then  
          mem_fpu_cmp_done <= false;
        elsif EX_PipeRun then
          mem_fpu_cmp_done <= ex_cmp_op and EX_Start_FPU;
        else
          mem_fpu_cmp_done <= false;
        end if;
      end if;
    end process MEM_FPU_Cmp_Done_DFF;

    -- This needs to be combinational
    mem_fpu_done_early <= ((mem_fpu_norm_delay(mem_fpu_norm_delay'right) = '1') or
                           mem_fpu_div_done or mem_fpu_cmp_done or mem_sqrt_done or mem_int_done or mem_flt_done);

    Using_FPU_Exception_1 : if (C_FPU_EXCEPTION > 0) generate

      Mem_FPU_Done_DFF: process (Clk) is
      begin  -- process Mem_FPU_Done_DFF
        if Clk'event and Clk = '1' then   -- rising clock edge
          if Reset = '1' then             -- synchronous reset (active high)
            mem_fpu_done_delay <= false;
          else
            mem_fpu_done_delay <= mem_fpu_done_early and mem_fpu_excep_early;
          end if;
        end if;
      end process Mem_FPU_Done_DFF;

      mem_fpu_done_i <= (mem_fpu_done_early and not mem_fpu_excep_early) or mem_fpu_done_delay;
    
    end generate Using_FPU_Exception_1;

    Not_Using_FPU_Exception_1 : if (C_FPU_EXCEPTION = 0) generate
      mem_fpu_done_i <= mem_fpu_done_early;
    end generate Not_Using_FPU_Exception_1;

    MEM_FPU_Done <= mem_fpu_done_i;
    
    -----------------------------------------------------------------------------
    -- MEM_FPU_Stall_DFF
    -- Indicates an FPU instruction stalled in the MEM stage
    -----------------------------------------------------------------------------
    MEM_FPU_Stall_DFF : process (Clk) is
    begin -- process MEM_FPU_Stall_DFF
      if Clk'event and Clk = '1' then  -- rising clock edge
        if Reset = '1' then  
          mem_fpu_stall_i    <= false;
        else
          if (mem_fpu_norm_delay(mem_fpu_norm_delay'right-1) = '1') then
            -- End of add/sub/mul
            mem_fpu_stall_i    <= false;
          elsif mem_fpu_div_done or mem_sqrt_done or mem_flt_done then
            -- End of div
            mem_fpu_stall_i    <= false;
          end if;
          if EX_PipeRun and EX_Start_FPU and not ex_cmp_op  then
            mem_fpu_stall_i    <= true;
          end if;
        end if;
      end if;
    end process MEM_FPU_Stall_DFF;

    -- Do not stall on the last cycle of an FPU divide instruction
    MEM_FPU_Stall <= mem_fpu_excep_early or (mem_fpu_stall_i and not mem_fpu_div_done and not mem_sqrt_done and not mem_flt_done);

    -- This shouldn't be necessary
    ex_a <= EX_Op2;
    ex_b <= EX_Op1;
  
    -----------------------------------------------------------------------------
    -- First stage
    -- The operands and operations are coming from DFFs in MicroBlaze's pipeline
    -----------------------------------------------------------------------------

    -- FPU Instruction?
    ex_not_fpu_instr_1 <= EX_Not_FPU_Instr;
  
    -- Op_1
    ex_fpu_op_1 <= EX_FPU_Op;
  
    -- Sign
    ex_SignA_1 <= ex_a(IEEE754_SINGLE_SIGN_POS);
    ex_SignB_1 <= ex_b(IEEE754_SINGLE_SIGN_POS);