fpu.vhd

Xilinx软核microblaze源码(VHDL)版本7.10

--SINGLE_FILE_TAG
-------------------------------------------------------------------------------
-- $Id: fpu.vhd,v 1.3 2007/11/07 12:47:48 stefana Exp $
-------------------------------------------------------------------------------
-- FPU - entity/architecture
-------------------------------------------------------------------------------
--
-- ****************************************************************************
-- ** Copyright(C) 2004-2005 by Xilinx, Inc. All rights reserved.
-- **
-- ** This text contains proprietary, confidential information of
-- ** Xilinx, Inc. , is distributed by under license from Xilinx, Inc.,
-- ** and may be used, copied and/or disclosed only pursuant to the
-- ** terms of a valid license agreement with Xilinx, Inc. 
-- **
-- ** Unmodified source code is guaranteed to place and route, 
-- ** function and run at speed according to the datasheet
-- ** specification. Source code is provided "as-is", with no
-- ** obligation on the part of Xilinx to provide support.
-- **
-- ** Xilinx Hotline support of source code IP shall only include
-- ** standard level Xilinx Hotline support, and will only address
-- ** issues and questions related to the standard released Netlist
-- ** version of the core (and thus indirectly, the original core source
-- **
-- ** The Xilinx Support Hotline does not have access to source
-- ** code and therefore cannot answer specific questions related
-- ** to source HDL. The Xilinx Support Hotline will only be able
-- ** to confirm the problem in the Netlist version of the core.
-- **
-- ** This copyright and support notice must be retained as part
-- ** of this text at all times.
-- ****************************************************************************
--
-------------------------------------------------------------------------------
-- Filename:        fpu.vhd
-- Version:         v2.00a
-- Description:     Implements an IEEE754-based single precision FPU
--                  
-------------------------------------------------------------------------------
-- Structure:   
--              fpu.vhd
--                - fpu_addsub.vhd
--                - fpu_mul.vhd
--                - fpu_div.vhd
--
-------------------------------------------------------------------------------
-- Author:          goran
-- Revision:        $Revision: 1.3 $
-- Date:            $Date: 2007/11/07 12:47:48 $
--
-- History:
--   goran  2004-07-01    First Version
--   BJS    2005-09-26
-- ^^^^^^
--                        Updated for new pipeline
-- ~~~~~~
--
-------------------------------------------------------------------------------
-- Naming Conventions:
--      active low signals:                     "*_n"
--      clock signals:                          "clk", "*_clk"
--      reset signals:                          "rst", "*_rst", "reset"
--      generics:                               All uppercase, starting with: "C_"
--      constants:                              All uppercase, not starting with: "C_"
--      state machine next state:               "*_next_state"
--      state machine current state:            "*_curr_state"
--      pipelined signals:                      "*_d#"
--      counter signals:                        "*_cnt_*" , "*_counter_*", "*_count_*"
--      internal version of output port:        "*_i"
--      ports:                                  Names begin with uppercase
--      component instantiations:               "<ENTITY>_I#|<FUNC>" , "<ENTITY>_I"
--
-- Signals starting with IF, OF, EX, MEM, or WB indicate that they start in that
-- stage:
--
--    IF                                -- instruction fetch
--    OF                                -- operand fetch
--    EX                                -- execute
--    MEM                               -- memory
--    WB                                -- write back
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

--------------------------------------------------------------------------
-- Include MicroBlaze package for data types and ISA constants
--------------------------------------------------------------------------
library Microblaze_v7_10_a;
use Microblaze_v7_10_a.MicroBlaze_ISA.all;
use Microblaze_v7_10_a.MicroBlaze_Types.all;

-- pragma xilinx_rtl_off
library unisim;
use unisim.vcomponents.all;
-- pragma xilinx_rtl_on

entity Fpu is
  generic (
    C_TARGET        : TARGET_FAMILY_TYPE := SPARTAN3E;
    C_USE_FPU       : integer := 2;  -- Enable FPU?
    C_FPU_EXCEPTION : integer := 0
  );
  port (
    Clk               : in  std_logic;  -- Clock
    Reset             : in  std_logic;  -- Reset
    OF_PipeRun        : in  boolean;    -- Move the operand fetch stage
    EX_PipeRun        : in  boolean;    -- Move the execute stage
    MEM_PipeRun       : in  boolean;    -- Move the memory stage
    EX_Op1            : in  DATA_TYPE;  -- First operand
    EX_Op2            : in  DATA_TYPE;  -- Second operand
    EX_FPU_Op         : in  FPU_OP_TYPE;    -- FPU operation
    EX_FPU_Cond       : in  FPU_COND_TYPE;  -- FPU comparison conditions
    EX_MTS_FSR        : in  std_logic;  -- MTS write to FSR
    EX_Start_FPU      : in  boolean;    -- Start the FPU
    EX_Not_FPU_Instr  : in  boolean;    -- Not an FPU instruction
    MEM_Not_FPU_Instr : in  boolean;    -- Not an FPU instruction
    MEM_Sel_SPR_FSR   : in  boolean;    -- Select SPR floating point status register
    MEM_FPU_Done      : out rboolean;   -- FPU is finished in the next cycle
    MEM_FPU_Stall     : out rboolean;   -- FPU is stalling Mem Stage
    MEM_FPU_Excep     : out rboolean;   -- FPU Exception
    WB_FPU_Excep      : out rboolean;   -- FPU Exception
    WB_FPU_Result     : out DATA_TYPE;  -- FPU Result
    WB_FSR            : out FSR_TYPE    -- FPU Status Register
  );
end entity Fpu;

architecture IMP of Fpu is

  component carry_compare is
    generic (
      C_TARGET : TARGET_FAMILY_TYPE;
      Size     : natural);
    port (
      A_Vec     : in  std_logic_vector(0 to Size-1);
      B_Vec     : in  std_logic_vector(0 to Size-1);
      Carry_In  : in  std_logic;
      Carry_Out : out std_logic);
  end component carry_compare;

  component carry_compare_const is
    generic (
      C_TARGET : TARGET_FAMILY_TYPE;
      Size     : natural;
      B_Vec    : std_logic_vector);
    port (
      A_Vec     : in  std_logic_vector(0 to Size-1);
      Carry_In  : in  std_logic;
      Carry_Out : out std_logic);
  end component carry_compare_const;

begin -- architecture IMP

  -- No FPU?
  No_FPU : if (C_USE_FPU = 0) generate
    MEM_FPU_Done  <= false;
    MEM_FPU_Stall <= false;
    MEM_FPU_Excep <= false;
    WB_FPU_Excep  <= false;
    WB_FPU_Result <= (others => '0');
    WB_FSR        <= (others => '0');
  end generate No_FPU;

  Use_FPU : if (C_USE_FPU /= 0) generate
    -- Mantissa is the term used in this file, it is called fraction in the
    -- IEEE754 specification, 
    -- Mantissa is also used in signal names that actually are the significand
    -- (they include the implicit bit)
  
    -----------------------------------------------------------------------------
    -- EX_FPU_Op
    -- 000 = Add (FPU /= 0)
    -- 001 = Sub (FPU /= 0)
    -- 010 = Mul (FPU /= 0)
    -- 011 = Div (FPU /= 0)
    -- 100 = CMP (FPU /= 0)
    -- 101 = FLT  (FPU = 2)
    -- 110 = INT  (FPU = 2)
    -- 111 = SQRT (FPU = 2)
    -----------------------------------------------------------------------------
  
    -----------------------------------------------------------------------------
    -- EX_FPU_Cond comparison conditions
    -- 001  Less Than
    -- 010  Equal
    -- 011  Less Than or Equal
    -- 100  Greater Than
    -- 101  Not Equal
    -- 110  Greater Than or Equal
    -- 000  UnOrdered
    -----------------------------------------------------------------------------
  
    -----------------------------------------------------------------------------
    -- FSR
    -- 27   IO   Invalid operation
    -- 28   DZ   Divide-by-zero
    -- 29   OF   Overflow
    -- 30   UF   Underflow
    -- 31   DO   Denormalized operand error
    -----------------------------------------------------------------------------
  
    -----------------------------------------------------------------------------
    -- FPU Flags
    -- 00001  Denormalized Inputs
    -- 00010  Underflow
    -- 00100  Overflow
    -- 01000  Div_By_0
    -- 10000  Invalid operation
    -----------------------------------------------------------------------------

    component FPU_ADDSUB is
      generic (
        C_TARGET              : TARGET_FAMILY_TYPE
      );
      port (
        Clk                   : in  std_logic;          -- Clock
        Reset                 : in  std_logic;          -- Reset
        MEM_Add_Op_2          : in  boolean;            -- Add operation
        MEM_Sub_Op_2          : in  boolean;            -- Subtract operation
        MEM_Add_Mant_2        : in  boolean;            -- Add or Subtract mantissa
        MEM_MantA_2           : in  FPU_MANT_I_TYPE;    -- Operand's A mantissa (with I)
        MEM_MantB_2           : in  FPU_MANT_I_TYPE;    -- Operand's A mantissa (with I)
        MEM_absAgtB_2         : in  boolean;            -- abs(OpA) > abs(OpB)
        MEM_Exp_absAsubB_2    : in  FPU_EXP_TYPE;       -- exponents abs(A - B)
        MEM_AddSub_Zero_4     : out boolean;            -- Mantissa is zero unless there is rounding
        MEM_AddSub_Inc_Exp_4  : out boolean;            -- Mul increment exponent
        MEM_AddSub_Sub_Exp_4  : out FPU_EXP_LS_TYPE;    -- Mantissa needed left shift, subtract exponent
        MEM_Mant_LS16_4       : out std_logic;          -- Result still needs to be shifted 16
        MEM_Mant_AddSub_Res_4 : out FPU_MANT_IGRS_TYPE  -- Result of addition/subtraction
      );
    end component FPU_ADDSUB;

    component FPU_MUL is
      generic (
        C_TARGET          : TARGET_FAMILY_TYPE
      );
      port (
        Clk               : in  std_logic;          -- Clock
        Reset             : in  std_logic;          -- Reset
        EX_MantA_1        : in  FPU_MANT_TYPE;      -- Operand A mantissa
        EX_MantB_1        : in  FPU_MANT_TYPE;      -- Operand B mantissa
        EX_PipeRun        : in  boolean;            -- Move the execute stage
        MEM_Mul_Res_4     : out FPU_MANT_IGRS_TYPE; -- FPU mantissa multiplicaiton result
        MEM_Mul_Inc_Exp_4 : out boolean             -- Mul increment exponent
      );
    end component FPU_MUL;

    component FPU_DIV is
      generic (
        C_TARGET          : TARGET_FAMILY_TYPE
      );
      port (
        Clk               : in  std_logic;          -- Clock
        Reset             : in  std_logic;          -- Reset
        EX_MantA_1        : in  FPU_MANT_TYPE;      -- Operand A mantissa
        EX_MantB_1        : in  FPU_MANT_TYPE;      -- Operand B mantissa
        EX_Start_FPU      : in  boolean;            -- Start the FPU
        EX_Div_Op         : in  boolean;            -- Is division operation?
        EX_PipeRun        : in  boolean;            -- Move the execute stage
        Mem_Not_Div_Op    : in  boolean;
        MEM_Div_Done      : out boolean;            -- FPU divider is done the next cycle
        MEM_Div_Res_4     : out FPU_MANT_IGRS_TYPE; -- FPU mantissa division result
        MEM_Div_Dec_Exp_4 : out boolean             -- Div decrement exponent
      );
    end component FPU_DIV;

    component fpu_sqrt is
      port (
        Clk               : in  std_logic;
        Reset             : in  std_logic;
        EX_Op1            : in  DATA_TYPE;
        EX_Sqrt_Op        : in  boolean;
        EX_Start_fpu      : in  boolean;
        EX_PipeRun        : in  boolean;
        MEM_Not_Sqrt_Op   : in  boolean;
        MEM_Sqrt_Done     : out boolean;
        MEM_Sqrt_Exp_4    : out FPU_EXP_TYPE;
        MEM_Sqrt_Result_4 : out FPU_MANT_IGRS_TYPE);
    end component fpu_sqrt;

    component fpu_conv is
      port (
        Clk                : in  std_logic;
        Reset              : in  std_logic;
        EX_PipeRun         : in  boolean;
        EX_Op1             : in  DATA_TYPE;
        EX_Op1_Mant_Zero   : in  boolean;
        EX_Flt_Op          : in  boolean;
        EX_Int_Op          : in  boolean;
        EX_Start_Fpu       : in  boolean;
        MEM_Flt_Done       : out boolean;
        MEM_Flt_Result_4   : out FPU_MANT_IGRS_TYPE;
        MEM_Flt_Exp_4      : out FPU_EXP_TYPE;
        MEM_Int_Done       : out boolean;
        MEM_Int_Done_Early : out boolean;
        Mem_Int_Zero_3     : out boolean;
        Mem_Int_Inv_3      : out boolean;
        MEM_Int_Result_5   : out DATA_TYPE);
    end component fpu_conv;
    
    -- subtype Exp_Plus1_T is std_logic_vector(FPU_EXP_TYPE'left to FPU_EXP_TYPE'right+1);
    -- subtype Exp_Plus3_T is std_logic_vector(FPU_EXP_TYPE'left to FPU_EXP_TYPE'right+3);
  
    -- Extra bits for when adding exponents for multiplication and to use carry to determine
    -- greater than
    subtype Exp_Plus2_T is std_logic_vector(FPU_EXP_TYPE'left to FPU_EXP_TYPE'right+2);
  
    -- Result Type
    subtype Result_T is std_logic_vector(0 to 7);
    constant Result_Invalid_POS   : natural := 0;
    constant Result_Nan_POS       : natural := 1;
    constant Result_Div0_POS      : natural := 2;
    constant Result_Overflow_POS  : natural := 3;
    constant Result_Underflow_POS : natural := 4;
    constant Result_DeNorm_POS    : natural := 5;
    constant Result_Inf_POS       : natural := 6;
    constant Result_Zero_POS      : natural := 7;
  
    -- Operation to perform
    signal ex_add_op  : boolean;
    signal ex_sub_op  : boolean;
    signal ex_mul_op  : boolean;
    signal ex_div_op  : boolean;
    signal ex_cmp_op  : boolean;
    signal ex_flt_op  : boolean;
    signal ex_int_op  : boolean;
    signal ex_sqrt_op : boolean;
  
    -- Internal operands
    signal ex_a      : DATA_TYPE;
    signal ex_b      : DATA_TYPE;
  
    -- Stage 1
    signal ex_not_fpu_instr_1 : boolean;
    signal ex_fpu_op_1        : FPU_OP_TYPE;
    signal ex_SignA_1         : std_logic;
    signal ex_ExpA_1          : FPU_EXP_TYPE;
    signal ex_MantA_1         : FPU_MANT_TYPE;