msr_reg.vhd

Xilinx软核microblaze源码(VHDL)版本7.10

--SINGLE_FILE_TAG
-------------------------------------------------------------------------------
-- $Id: msr_reg.vhd,v 1.1 2007/10/12 09:11:36 stefana Exp $
-------------------------------------------------------------------------------
-- MSR_Reg - entity/architecture 
-------------------------------------------------------------------------------
--
--                  ****************************
--                  ** Copyright Xilinx, Inc. **
--                  ** All rights reserved.   **
--                  ****************************
--
-------------------------------------------------------------------------------
-- Filename:        msr_reg.vhd
-- Version:         v1.00a
-- Description:     Implements the MSR Register
--                  
-------------------------------------------------------------------------------
-- Structure:   
--              msr_reg.vhd
--
-------------------------------------------------------------------------------
-- Author:          goran
-- History:
--   goran  2001-03-05    First Version
--
-------------------------------------------------------------------------------
-- Naming Conventions:
--      active low signals:                     "*_n"
--      clock signals:                          "clk", "clk_div#", "clk_#x" 
--      reset signals:                          "rst", "rst_n" 
--      generics:                               "C_*" 
--      user defined types:                     "*_TYPE" 
--      state machine next state:               "*_ns" 
--      state machine current state:            "*_cs" 
--      combinatorial signals:                  "*_com" 
--      pipelined or register delay signals:    "*_d#" 
--      counter signals:                        "*cnt*"
--      clock enable signals:                   "*_ce" 
--      internal version of output port         "*_i"
--      device pins:                            "*_pin" 
--      ports:                                  - Names begin with Uppercase 
--      processes:                              "*_PROCESS" 
--      component instantiations:               "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------

library IEEE;
use IEEE.std_logic_1164.all;

library Microblaze_v7_10_a;
use Microblaze_v7_10_a.MicroBlaze_ISA.all;
use Microblaze_v7_10_a.MicroBlaze_Types.all;

-------------------------------------------------------------------------------
-- Port declarations
-------------------------------------------------------------------------------

entity MSR_Reg is
  generic (
    -- Size generics
    C_TARGET         : TARGET_FAMILY_TYPE;
    C_RESET_MSR      : MSR_TYPE := (others => '0');
    C_PVR            : integer  := 0;
    C_USE_DIV        : boolean  := false;
    C_USE_D_OPB      : boolean  := false;
    C_FSL_LINKS      : integer  := 0;
    C_USE_ICACHE     : boolean  := false;
    C_USE_DCACHE     : boolean  := false;
    C_DATA_SIZE      : natural  := 32;
    C_USE_MSR_INSTR  : integer  := 0;
    C_USE_EXCEPTIONS : boolean  := false
    );
  port (
    Clk   : in std_logic;
    Reset : in boolean;

    Write_Carry        : in  boolean;
    New_Carry          : in  std_logic;
    MTS_Write          : in  boolean;
    Disable_Interrupts : in  boolean;
    Enable_Interrupts  : in  boolean;
    Set_BIP            : in  boolean;
    Reset_BIP          : in  boolean;
    Disable_Exceptions : in  boolean;
    Enable_Exceptions  : in  boolean;
    Set_EIP            : in  boolean;
    Reset_EIP          : in  boolean;
    FSL_Write_Carry    : in  std_logic;
    FSL_Carry          : in  std_logic;
    Div_By_Zero        : in  std_logic;
    Set_FSL_Error      : in  boolean;
    Op1                : in  std_logic_vector(C_DATA_SIZE-MSR_REG_TYPE'length to C_DATA_SIZE-1);
    Op2                : in  std_logic_vector(C_DATA_SIZE-MSR_REG_TYPE'length to C_DATA_SIZE-1);
    MSRxxx_Instr       : in  boolean;
    MSRclr_Instr       : in  boolean;
    MSR                : out MSR_REG_TYPE
    );

end entity MSR_Reg;

-------------------------------------------------------------------------------
-- Architecture section
-------------------------------------------------------------------------------

architecture IMP of MSR_Reg is

  component MSR_Reg_Bit is
    generic (
      C_TARGET : TARGET_FAMILY_TYPE);
    port (
      Clk : in std_logic;
      -- Reset : in boolean;

      Write_MSR : in  std_logic;
      New_Value : in  std_logic;
      MSR_Rst   : in  std_logic;
      MSR_Set   : in  std_logic;
      MSR       : out std_logic);
  end component MSR_Reg_Bit;

  -- Types and constants
  subtype MSR_NOPVR_REG_POS_TYPE is
    natural range MSR_REG_TYPE'left+1 to MSR_REG_TYPE'right;
  subtype MSR_NOPVR_REG_TYPE is
    std_logic_vector(MSR_NOPVR_REG_POS_TYPE);

  constant Has_MSR_Reg_Bit : boolean_array(MSR_NOPVR_REG_POS_TYPE) := (
    MSR_BE_POS  => C_USE_D_OPB,
    MSR_IE_POS  => true,
    MSR_C_POS   => true,
    MSR_BIP_POS => true,
    MSR_FSL_POS => C_FSL_LINKS > 0,
    MSR_ICE_POS => C_USE_ICACHE,
    MSR_DZ_POS  => C_USE_DIV,
    MSR_DCE_POS => C_USE_DCACHE,
    MSR_EE_POS  => C_USE_EXCEPTIONS,
    MSR_EIP_POS => C_USE_EXCEPTIONS);

  -- Signals
  signal rst_Values    : MSR_NOPVR_REG_TYPE;
  signal rst_Values_I  : MSR_NOPVR_REG_TYPE;
  signal rst_Values_II : MSR_NOPVR_REG_TYPE;
  signal set_Values    : MSR_NOPVR_REG_TYPE;
  signal set_Values_I  : MSR_NOPVR_REG_TYPE;
  signal we_Bits       : MSR_NOPVR_REG_TYPE;
  signal new_Value_I   : MSR_NOPVR_REG_TYPE;

  signal msr_I : MSR_REG_TYPE;

-------------------------------------------------------------------------------
-- Begin architecture
-------------------------------------------------------------------------------

begin  -- architecture IMP

  -- Buslock enable
  rst_Values(MSR_BE_POS) <= '0';
  set_Values(MSR_BE_POS) <= '0';

  -- Interrupt enable
  rst_Values(MSR_IE_POS) <= '1' when Disable_Interrupts else '0';
  set_Values(MSR_IE_POS) <= '1' when Enable_Interrupts  else '0';

  -- Arithmetic carry
  -- This is treated specially below
  rst_Values(MSR_C_POS) <= '0';
  -- set_Values(MSR_C_POS) <= '0';

  -- Break in progress
  rst_Values(MSR_BIP_POS) <= '1' when Reset_BIP else '0';
  set_Values(MSR_BIP_POS) <= '1' when Set_BIP   else '0';

  -- FSL error
  set_Values(MSR_FSL_POS) <= '1' when Set_FSL_Error else '0';
  rst_Values(MSR_FSL_POS) <= '0';

  -- Instruction cache enable
  rst_Values(MSR_ICE_POS) <= '0';
  set_Values(MSR_ICE_POS) <= '0';

  -- Division by zero
  set_Values(MSR_DZ_POS) <= Div_By_Zero;
  rst_Values(MSR_DZ_POS) <= '0';

  -- Data cache enable
  rst_Values(MSR_DCE_POS) <= '0';
  set_Values(MSR_DCE_POS) <= '0';

  -- Exception enable
  rst_Values(MSR_EE_POS) <= '1' when Disable_Exceptions else '0';
  set_Values(MSR_EE_POS) <= '1' when Enable_Exceptions  else '0';

  -- Exception in progress
  rst_Values(MSR_EIP_POS) <= '1' when Reset_EIP else '0';
  set_Values(MSR_EIP_POS) <= '1' when Set_EIP   else '0';

  -- PVR
  msr_I(MSR_PVR_POS) <= '1' when (C_PVR /= C_PVR_NONE) else '0';

  Fixing_Writes_And_Values : process (FSL_Carry, FSL_Write_Carry, New_Carry, Op1, rst_Values,
                                      Write_Carry, MTS_Write, MSRxxx_Instr, MSRclr_Instr, Op2, Reset) is
    variable local_rst_values : MSR_NOPVR_REG_TYPE;
  begin  -- process Fixing_Writes_And_Values

    local_rst_values := rst_Values;

    -- Op1 used for MTS rmsr instruction
    -- Op2 used as New_Value in other cases
    new_Value_I <= Op1(Op1'right-new_Value_I'length+1 to Op1'right);

    -- Default assignment
    if (MTS_Write) then
      we_Bits <= (others => '1');
    else
      we_Bits <= (others => '0');
    end if;

    -- The BIP value can't be set using the MTS instruction
    -- Allowing the writing the BIP again
    -- It was done previously for helping xmdstub but the use of xmdstub
    -- is now less due to the HW debug
    -- we_Bits(MSR_BIP_POS) <= '0';

    -- Special Treatmeant for Carry
    if (Write_Carry) then
      local_rst_Values(MSR_C_POS) := not New_Carry;
      set_Values(MSR_C_POS) <= '1';
    else
      local_rst_Values(MSR_C_POS) := '0';
      set_Values(MSR_C_POS) <= '0';
    end if;

    if (FSL_Write_Carry = '1') then
      we_Bits(MSR_C_POS)     <= '1';
      new_Value_I(MSR_C_POS) <= FSL_Carry;
    end if;

    if (C_USE_MSR_INSTR /= 0) then

      -- Forward the carry bit
      if (MSRxxx_Instr) then
        if (MSRclr_Instr) and (Op2(MSR_C_POS) = '1') then
          we_Bits(MSR_C_POS)     <= '1';
          new_Value_I(MSR_C_POS) <= '0';
        end if;
        if (not MSRclr_Instr) and (Op2(MSR_C_POS) = '1') then
          we_Bits(MSR_C_POS)     <= '1';
          new_Value_I(MSR_C_POS) <= '1';
        end if;
      end if;

    end if;

    if (Reset) then
      for I in MSR_NOPVR_REG_POS_TYPE'left to MSR_NOPVR_REG_POS_TYPE'right loop
        rst_Values_II(I) <= not C_RESET_MSR(I);
      end loop;  -- I
    else
      rst_Values_II <= local_rst_Values;
    end if;
  end process Fixing_Writes_And_Values;

  Using_MSRxxx_Instr : if (C_USE_MSR_INSTR /= 0) generate

    Handle_MSRxxx_Instr : process (MSRclr_Instr, MSRxxx_Instr, Op2, rst_Values_II,
                                   set_Values, reset) is
      variable clr_MSR : boolean;
      variable set_MSR : boolean;
    begin  -- process Handle_MSRxxx_Instr
      clr_MSR := MSRxxx_Instr and MSRclr_Instr;
      set_MSR := MSRxxx_Instr and not MSRclr_Instr;

      if (clr_MSR) then
        rst_Values_I <= Op2(Op2'right-rst_Values_I'length+1 to Op2'right);
      else
        rst_Values_I <= rst_Values_II;
      end if;
      if (set_MSR) then
        set_Values_I <= Op2(Op2'right-set_Values_I'length+1 to Op2'right);
      else
        set_Values_I <= set_Values;        
      end if;

      -- The carry bit is handled differently
      rst_Values_I(MSR_C_POS) <= rst_Values_II(MSR_C_POS);
      set_Values_I(MSR_C_POS) <= set_Values(MSR_C_POS);
      if (Reset) then
        for I in MSR_NOPVR_REG_POS_TYPE'left to MSR_NOPVR_REG_POS_TYPE'right loop
          if (C_RESET_MSR(I) = '1') then
            set_Values_I(I) <= '1';
          end if;
        end loop;  -- I
      end if;      
    end process Handle_MSRxxx_Instr;

  end generate Using_MSRxxx_Instr;

  No_MSRxxx_Instr : if (C_USE_MSR_INSTR = 0) generate
    rst_Values_I <= rst_Values_II;

    Set_Values_Reset_Handling: process (reset,set_Values) is
    begin  -- process Set_Values_Reset_Handling
      set_Values_I <= set_Values;
      if (Reset) then
        for I in MSR_NOPVR_REG_POS_TYPE'left to MSR_NOPVR_REG_POS_TYPE'right loop
          if (C_RESET_MSR(I) = '1') then
            set_Values_I(I) <= '1';
          end if;
        end loop;  -- I
      end if;            
    end process Set_Values_Reset_Handling;
  end generate No_MSRxxx_Instr;

  Using_FPGA : if (C_TARGET /= RTL) generate
    MSR_Bits : for I in MSR_NOPVR_REG_TYPE'left to MSR_NOPVR_REG_TYPE'right generate
      Using_MSR_Reg_Bit : if Has_MSR_Reg_Bit(I) generate
        MSR_Reg_Bit_I : MSR_Reg_Bit
          generic map (
            C_TARGET => C_TARGET)
          port map (
            Clk       => Clk,              -- [in]
            -- Reset     => Reset,            -- [in]
            Write_MSR => we_Bits(I),       -- [in]
            MSR_Rst   => rst_Values_I(I),  -- [in]
            MSR_Set   => set_Values_I(I),  -- [in]
            New_Value => new_Value_I(I),   -- [in]
            MSR       => msr_I(I));        -- [out]
      end generate Using_MSR_Reg_Bit;

      No_MSR_Reg_Bit : if (not Has_MSR_Reg_Bit(I)) generate
        msr_I(I) <= '0';
      end generate No_MSR_Reg_Bit;
    end generate MSR_Bits;
  end generate Using_FPGA;

  Using_RTL : if (C_TARGET = RTL) generate

    MSR_Handle : process (Reset, Clk) is
    begin  -- process MSR_Handle
      if Clk'event and Clk = '1' then  -- rising clock edge
        if (Reset) then
          MSR_I <= C_RESET_MSR(MSR_REG_TYPE'range);
        else
          for I in MSR_NOPVR_REG_TYPE'left to MSR_NOPVR_REG_TYPE'right loop
            if (not Has_MSR_Reg_Bit(I)) then
              MSR_I(I) <= '0';
            elsif (rst_Values_I(I) = '1') then
              MSR_I(I) <= '0';
            elsif (set_Values_I(I) = '1') then
              MSR_I(I) <= '1';
            elsif (we_Bits(I) = '1') then
              MSR_I(I) <= new_Value_I(I);
            end if;
          end loop;
        end if;
      end if;
    end process MSR_Handle;

  end generate Using_RTL;

  MSR <= msr_I;

end architecture IMP;