carry_compare_const.vhd

Xilinx软核microblaze源码(VHDL)版本7.10

-------------------------------------------------------------------------------
-- $Id: carry_compare_const.vhd,v 1.2 2007/11/09 13:06:27 stefana Exp $
-------------------------------------------------------------------------------
-- Carry_compare_const.vhd - Entity and architecture
--
--  ***************************************************************************
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--
-------------------------------------------------------------------------------
-- Filename:        carry_compare_const.vhd
--
-- Description:     
--                  
-- VHDL-Standard:   VHDL'93
-------------------------------------------------------------------------------
-- Structure:   
--              carry_compare_const.vhd
--
-------------------------------------------------------------------------------
-- Author:          stefana
-- Revision:        $Revision: 1.2 $
-- Date:            $Date: 2007/11/09 13:06:27 $
--
-- History:
--   stefana    2007-10-22    First Version
--
-------------------------------------------------------------------------------
-- Naming Conventions:
--      active low signals:                     "*_n"
--      clock signals:                          "clk", "clk_div#", "clk_#x" 
--      reset signals:                          "rst", "rst_n" 
--      generics:                               "C_*" 
--      user defined types:                     "*_TYPE" 
--      state machine next state:               "*_ns" 
--      state machine current state:            "*_cs" 
--      combinatorial signals:                  "*_com" 
--      pipelined or register delay signals:    "*_d#" 
--      counter signals:                        "*cnt*"
--      clock enable signals:                   "*_ce" 
--      internal version of output port         "*_i"
--      device pins:                            "*_pin" 
--      ports:                                  - Names begin with Uppercase 
--      processes:                              "*_PROCESS" 
--      component instantiations:               "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
library Microblaze_v7_10_a;
use Microblaze_v7_10_a.MicroBlaze_Types.all;

entity carry_compare_const is
  generic (
    C_TARGET : TARGET_FAMILY_TYPE;
    Size     : natural;
    B_Vec    : std_logic_vector);
  port (
    A_Vec     : in  std_logic_vector(0 to Size-1);
    Carry_In  : in  std_logic;
    Carry_Out : out std_logic);
end entity carry_compare_const;

library unisim;
use unisim.vcomponents.all;

architecture IMP of carry_compare_const is

  component carry_and is
    generic (
      C_TARGET : TARGET_FAMILY_TYPE);
    port (
      Carry_IN  : in  std_logic;
      A         : in  std_logic;
      Carry_OUT : out std_logic);
  end component carry_and;

  -- 6-LUT architectures can't pack more than 4 bits/LUT without size increase
  constant C_BITS_PER_LUT : integer := 4;
  constant C_NR_OF_LUTS   : integer :=
    (Size + (C_BITS_PER_LUT - 1)) / C_BITS_PER_LUT;

  signal sel   : std_logic_vector(0 to C_NR_OF_LUTS - 1);
  signal carry : std_logic_vector(0 to C_NR_OF_LUTS);

begin  -- architecture IMP

  carry(carry'right) <= Carry_In;

  The_Compare : for I in sel'right downto sel'left generate
  begin
    -- Combine the signals that fit into one LUT.
    --   sel(I) <= (A_Vec(2*I)   xnor B_Vec(2*I)) and
    --             (A_Vec(2*I+1) xnor B_Vec(2*I+1));
    Compare_All_Bits: process(A_Vec)
      variable sel_I : std_logic;
    begin
      sel_I := '1';
      Compare_Bits: for J in C_BITS_PER_LUT - 1 downto 0 loop
        if C_BITS_PER_LUT * I + J < Size then
          sel_I := sel_I and ( A_Vec(A_Vec'left + C_BITS_PER_LUT * I + J) xnor
                               B_Vec(B_Vec'left + C_BITS_PER_LUT * I + J) );
        end if;
      end loop Compare_Bits;
      sel(I) <= sel_I;
    end process Compare_All_Bits;

    carry_and_I1: carry_and
      generic map (
        C_TARGET => C_TARGET)     -- [TARGET_FAMILY_TYPE]
      port map (
        Carry_IN  => Carry(I+1),  -- [in  std_logic]
        A         => sel(I),      -- [in  std_logic]
        Carry_OUT => Carry(I));   -- [out std_logic]

  end generate The_Compare;

  Carry_Out <= Carry(0);

end architecture IMP;