mmu_utlb_ram.vhd

Xilinx软核microblaze源码(VHDL)版本7.10

-------------------------------------------------------------------------------
-- $Id: mmu_utlb_ram.vhd,v 1.1 2007/10/12 09:11:36 stefana Exp $
-------------------------------------------------------------------------------
-- mmu_utlb_ram.vhd - Entity and architecture
--
--  ***************************************************************************
--  **  Copyright(C) 2007 by Xilinx, Inc. All rights reserved.               **
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--  **  obligation on the part of Xilinx to provide support.                 **
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--  **  Xilinx Hotline support of source code IP shall only include          **
--  **  standard level Xilinx Hotline support, and will only address         **
--  **  issues and questions related to the standard released Netlist        **
--  **  version of the core (and thus indirectly, the original core source). **
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--  ***************************************************************************
--
-------------------------------------------------------------------------------
-- Filename:        mmu_utlb_ram.vhd
--
-- Description:     This file contains an implementation of the unified Memory
--                  Management Unit Translation Look-aside Buffer block RAM.
--
-- VHDL-Standard:   VHDL'93/02
-------------------------------------------------------------------------------
-- Structure:   
--              mmu_utlb_ram.vhd
--
-------------------------------------------------------------------------------
-- Author:          stefana
-- Revision:        $Revision: 1.1 $
-- Date:            $Date: 2007/10/12 09:11:36 $
--
-- History:
--   stefana 2007-02-16    First Version
--
-------------------------------------------------------------------------------
-- Naming Conventions:
--      active low signals:                     "*_n"
--      clock signals:                          "clk", "clk_div#", "clk_#x" 
--      reset signals:                          "rst", "rst_n" 
--      generics:                               "C_*" 
--      user defined types:                     "*_TYPE" 
--      state machine next state:               "*_ns" 
--      state machine current state:            "*_cs" 
--      combinatorial signals:                  "*_com" 
--      pipelined or register delay signals:    "*_d#" 
--      counter signals:                        "*cnt*"
--      clock enable signals:                   "*_ce" 
--      internal version of output port         "*_i"
--      device pins:                            "*_pin" 
--      ports:                                  - Names begin with Uppercase 
--      processes:                              "*_PROCESS" 
--      component instantiations:               "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;

entity MMU_UTLB_RAM is
  port(
    clka  : in std_logic;
    clkb  : in std_logic;
    ena   : in std_logic;
    enb   : in std_logic;
    wea   : in std_logic;
    web   : in std_logic;
    addra : in std_logic_vector(8 downto 0);
    addrb : in std_logic_vector(8 downto 0);
    dia   : in std_logic_vector(35 downto 0);
    dib   : in std_logic_vector(35 downto 0);
    doa   : out std_logic_vector(35 downto 0);
    dob   : out std_logic_vector(35 downto 0)
  );
end MMU_UTLB_RAM;

library IEEE;
use IEEE.numeric_std.all;

architecture IMP of MMU_UTLB_RAM is
  type ram_type is array (511 downto 0) of std_logic_vector(35 downto 0);
  shared variable RAM : ram_type;
begin

  process (CLKA)
  begin
    if CLKA'event and CLKA = '1' then
      if ENA = '1' then
        if WEA = '1' then
          RAM(to_integer(unsigned(ADDRA))) := DIA;
        end if;
        DOA <= RAM(to_integer(unsigned(ADDRA)));
      end if;
    end if;
  end process;

  process (CLKB)
  begin
    if CLKB'event and CLKB = '1' then
      if ENB = '1' then
        if WEB = '1' then
          RAM(to_integer(unsigned(ADDRB))) := DIB;
        end if;
        DOB <= RAM(to_integer(unsigned(ADDRB)));
      end if;
    end if;
  end process;

end IMP;