pvr.vhd

Xilinx软核microblaze源码(VHDL)版本7.10

      return '1';
    end if;
  end function int2std;

  function log2(x : natural) return integer is
    variable i : integer := 0;
  begin
    if x = 0 then return 0;
    else
      while 2**i < x loop
        i := i+1;
      end loop;
      return i;
    end if;
  end function log2;

  function Populate_PVR return PVR_Array_Type is
    variable PVR : PVR_Array_Type;
  begin
    -- PVR0
    if C_PVR = C_PVR_BASIC then
      PVR(0)(0) := '0';
    else -- C_PVR_FULL
      PVR(0)(0) := '1';
    end if;
    PVR(0)(1)        := int2std(BOOLEAN'POS(C_USE_BARREL));
    PVR(0)(2)        := int2std(BOOLEAN'POS(C_USE_DIV));
    PVR(0)(3)        := int2std(BOOLEAN'POS(C_USE_HW_MUL or C_USE_MUL64));
    PVR(0)(4)        := int2std(C_USE_FPU);
    PVR(0)(5)        := int2std(C_UNALIGNED_EXCEPTIONS) or
                        int2std(C_ILL_OPCODE_EXCEPTION) or
                        int2std(C_IOPB_BUS_EXCEPTION) or
                        int2std(C_DOPB_BUS_EXCEPTION) or
                        int2std(C_IPLB_BUS_EXCEPTION) or
                        int2std(C_DPLB_BUS_EXCEPTION) or
                        int2std(C_DIV_ZERO_EXCEPTION) or
                        int2std(C_FPU_EXCEPTION) or
                        int2std(C_FSL_EXCEPTION) or
                        int2std(C_USE_MMU);
    PVR(0)(6)        := int2std(C_USE_ICACHE);
    PVR(0)(7)        := int2std(C_USE_DCACHE);
    PVR(0)(8)        := int2std(C_USE_MMU);
    PVR(0)(9 to 15)  := (others => '0');
    PVR(0)(16 to 23) := C_MB_VERSION;
    PVR(0)(24 to 31) := C_PVR_USER1;

    -- PVR1
    PVR(1)           := C_PVR_USER2;
    
    -- PVR2
    PVR(2)(0)        := int2std(C_D_OPB);
    PVR(2)(1)        := int2std(C_D_LMB);
    PVR(2)(2)        := int2std(C_I_OPB);
    PVR(2)(3)        := int2std(C_I_LMB);
    PVR(2)(4)        := int2std(C_INTERRUPT_IS_EDGE);
    PVR(2)(5)        := int2std(C_EDGE_IS_POSITIVE);
    PVR(2)(6)        := int2std(C_D_PLB);
    PVR(2)(7)        := int2std(C_I_PLB);
    PVR(2)(8)        := int2std(C_INTERCONNECT);
    PVR(2)(9 to 11)  := (others => '0');
    PVR(2)(12)       := int2std(C_USE_EXTENDED_FSL_INSTR);
    PVR(2)(13)       := int2std(C_FSL_EXCEPTION);
    PVR(2)(14)       := int2std(BOOLEAN'POS(C_USE_MSR_INSTR));
    PVR(2)(15)       := int2std(BOOLEAN'POS(C_USE_PCMP_INSTR));
    PVR(2)(16)       := int2std(BOOLEAN'POS(C_AREA_OPTIMIZED));
    PVR(2)(17)       := int2std(BOOLEAN'POS(C_USE_BARREL));
    PVR(2)(18)       := int2std(BOOLEAN'POS(C_USE_DIV));
    PVR(2)(19)       := int2std(BOOLEAN'POS(C_USE_HW_MUL));
    PVR(2)(20)       := int2std(C_USE_FPU);
    PVR(2)(21)       := int2std(BOOLEAN'POS(C_USE_MUL64));
    PVR(2)(22)       := int2std(C_USE_FPU/2);
    PVR(2)(23)       := int2std(C_IPLB_BUS_EXCEPTION);
    PVR(2)(24)       := int2std(C_DPLB_BUS_EXCEPTION);
    PVR(2)(25)       := int2std(C_OPCODE_0x0_ILLEGAL);
    PVR(2)(26)       := int2std(C_UNALIGNED_EXCEPTIONS);
    PVR(2)(27)       := int2std(C_ILL_OPCODE_EXCEPTION);
    PVR(2)(28)       := int2std(C_IOPB_BUS_EXCEPTION);
    PVR(2)(29)       := int2std(C_DOPB_BUS_EXCEPTION);
    PVR(2)(30)       := int2std(C_DIV_ZERO_EXCEPTION);
    PVR(2)(31)       := int2std(C_FPU_EXCEPTION);

    -- PVR3
    PVR(3)(0)        := int2std(C_DEBUG_ENABLED);
    PVR(3)(1 to 2)   := (others => '0');
    PVR(3)(3 to 6)   := std_logic_vector(TO_UNSIGNED(C_NUMBER_OF_PC_BRK,4));
    PVR(3)(7 to 9)   := (others => '0');
    PVR(3)(10 to 12) := std_logic_vector(TO_UNSIGNED(C_NUMBER_OF_RD_ADDR_BRK,3));
    PVR(3)(13 to 15) := (others => '0');
    PVR(3)(16 to 18) := std_logic_vector(TO_UNSIGNED(C_NUMBER_OF_WR_ADDR_BRK,3));
    PVR(3)(19 to 20) := (others => '0');
    PVR(3)(21 to 24) := std_logic_vector(TO_UNSIGNED(C_FSL_LINKS,4));
    PVR(3)(25 to 31) := (others => '0');
    
    -- PVR4
    PVR(4)(0)        := int2std(C_USE_ICACHE);
    PVR(4)(1 to 5)   := std_logic_vector(TO_UNSIGNED(C_ADDR_TAG_BITS,5));
    PVR(4)(6)        := int2std(C_ICACHE_USE_FSL);
    PVR(4)(7)        := int2std(C_ALLOW_ICACHE_WR);
    PVR(4)(8 to 10)  := std_logic_vector(TO_UNSIGNED(log2(C_ICACHE_LINE_LEN),3));
    PVR(4)(11 to 15) := std_logic_vector(TO_UNSIGNED(log2(C_CACHE_BYTE_SIZE),5));
    PVR(4)(16)       := int2std(C_ICACHE_ALWAYS_USED);
    PVR(4)(17 to 31) := (others => '0');
    
    -- PVR5
    PVR(5)(0)        := int2std(C_USE_DCACHE);
    PVR(5)(1 to 5)   := std_logic_vector(TO_UNSIGNED(C_DCACHE_ADDR_TAG,5));
    PVR(5)(6)        := int2std(C_DCACHE_USE_FSL);
    PVR(5)(7)        := int2std(C_ALLOW_DCACHE_WR);
    PVR(5)(8 to 10)  := std_logic_vector(TO_UNSIGNED(log2(C_DCACHE_LINE_LEN),3));
    PVR(5)(11 to 15) := std_logic_vector(TO_UNSIGNED(log2(C_DCACHE_BYTE_SIZE),5));
    PVR(5)(16)       := int2std(C_DCACHE_ALWAYS_USED);
    PVR(5)(17 to 31) := (others => '0');

    -- PVR6
    PVR(6)           := C_ICACHE_BASEADDR;
    
    -- PVR7
    PVR(7)           := C_ICACHE_HIGHADDR;

    -- PVR8
    PVR(8)           := C_DCACHE_BASEADDR;
    
    -- PVR9
    PVR(9)           := C_DCACHE_HIGHADDR;

    -- PVR10
    PVR(10)(0 to 7)  := std_logic_vector(TO_UNSIGNED(TARGET_FAMILY_TYPE'POS(C_TARGET),8));
    PVR(10)(8 to 31) := (others => '0');
    
    -- PVR11
    PVR(11)(0 to 1)   := std_logic_vector(TO_UNSIGNED(C_USE_MMU,2));
    PVR(11)(2 to 4)   := std_logic_vector(TO_UNSIGNED(log2(C_MMU_ITLB_SIZE),3));
    PVR(11)(5 to 7)   := std_logic_vector(TO_UNSIGNED(log2(C_MMU_DTLB_SIZE),3));
    PVR(11)(8 to 9)   := std_logic_vector(TO_UNSIGNED(C_MMU_TLB_ACCESS,2));
    PVR(11)(10 to 14) := std_logic_vector(TO_UNSIGNED(C_MMU_ZONES,5));

    PVR(11)(15 to MSR_REG_POS_TYPE'LOW-1) := (others => '0');
    PVR(11)(MSR_REG_POS_TYPE)             := C_RESET_MSR;

    -- PVR12-15
    PVR(12) := (others => '0');
    PVR(13) := (others => '0');
    PVR(14) := (others => '0');
    PVR(15) := (others => '0');
    
    return PVR;
  end;
  
  constant PVR : PVR_Array_Type := Populate_PVR;  -- Populate PVR look-up table
    
begin

  -- None PVR drive all zero's
  None: if C_PVR = C_PVR_NONE generate
  begin
    WB_PVR <= (others => '0');
  end generate None;                       

  
  -- Basic PVR 
  Basic: if C_PVR = C_PVR_BASIC generate
    PVR_REG : process (Clk) is
    begin -- process PVR_REG
      if Clk'event and Clk = '1' then
        if Reset = '1' or not MEM_Sel_SPR_PVR then
          WB_PVR <= (others => '0');
        elsif MEM_PipeRun then
          WB_PVR <= PVR(0);
        end if;
      end if;
    end process PVR_REG;
  end generate Basic;

  -- Full PVR 
  Full: if C_PVR = C_PVR_FULL generate
  
    signal WB_PVR_I     : PVR_TYPE;

    attribute rom_style: string;
    attribute rom_style of WB_PVR_I: signal is "distributed";
    
  begin
    PVR_REG : process (Clk) is
    begin -- process PVR_REG
      if Clk'event and Clk = '1' then
        if Reset = '1' or not MEM_Sel_SPR_PVR then
          WB_PVR_I <= (others => '0');
        elsif MEM_PipeRun then
          WB_PVR_I <= PVR(TO_INTEGER(UNSIGNED(MEM_PVR_Select)));
        end if;
      end if;
    end process PVR_REG;
    
    WB_PVR  <= WB_PVR_I;
  end generate Full;                       
            
end architecture IMP;