msr_reg_gti.vhd

Xilinx软核microblaze源码(VHDL)版本7.10

      elsif mem_piperun then
        mem_msr_i <= mem_msr_cmb;
      end if;
    end if;
  end process mem_msr_FF;

  -----------------------------------------------------------------------------
  -- EX stage
  -----------------------------------------------------------------------------
  ex_msr_handler: process ( EX_ALU_Carry, EX_FSL_Carry, EX_FSL_Control_Error,
                            EX_MSRCLR, EX_MSRSET, EX_MSR_Clear_BIP,
                            EX_MSR_Clear_VM_UM,
                            EX_MSR_Clear_EIP, EX_MSR_Load_ALU_C,
                            EX_MSR_Load_FSL_C,
                            EX_MSR_Load_Shift_C, EX_MSR_Set_EE, EX_MSR_Set_IE,
                            EX_MSR_Set_SW_BIP, EX_MTS_MSR, EX_Op1, EX_Op2,
                            EX_Shift_Carry, MEM_DivideByZero, ex_MSR_i)
  begin  -- process ex_msr_handler
    -- default assignment
    ex_MSR_cmb <= ex_MSR_i;

    -- MEM stage MSR forwarding:
    -- only need to forward the DZ bit from MEM_MSR
    if MEM_DivideByZero then
      ex_MSR_cmb(MSR_DZ_POS) <= '1';
    end if;

    -- EX stage MSR effects
    if EX_MTS_MSR = '1' then
      ex_MSR_cmb <= EX_Op1(MSR_REG_POS_TYPE);
    elsif EX_MSRSET = '1' then
      ex_MSR_cmb <= ex_MSR_i or EX_Op2(MSR_REG_POS_TYPE);
    elsif EX_MSRCLR = '1' then
      ex_MSR_cmb <= ex_MSR_i and not EX_Op2(MSR_REG_POS_TYPE);
    end if;

    -- Load Carry bit
    if EX_MSR_Load_ALU_C = '1' then
      ex_msr_cmb(MSR_C_POS) <= EX_ALU_Carry;
    elsif EX_MSR_Load_Shift_C = '1' then
      ex_msr_cmb(MSR_C_POS) <= EX_Shift_Carry;
    elsif EX_MSR_Load_FSL_C = '1' then
      ex_msr_cmb(MSR_C_POS) <= EX_FSL_Carry;
    end if;

    -- set BIP bit for BRK/BRKI instructions
    -- Done in EX because of BRK instruction is implemented as normal jump
    -- (will not flush pipeline after propagating to WB stage).
    if EX_MSR_Set_SW_BIP = '1' then
      ex_msr_cmb(MSR_BIP_POS) <= '1';
    elsif EX_MSR_Clear_BIP = '1' then
      ex_msr_cmb(MSR_BIP_POS) <= '0';
    end if;

    -- set EE bit
    if EX_MSR_Set_EE = '1' then
      ex_msr_cmb(MSR_EE_POS) <= '1';
    end if;

    -- set EE bit
    if EX_MSR_Set_IE = '1' then
      ex_msr_cmb(MSR_IE_POS) <= '1';
    end if;

    -- clear EIP bit
    if EX_MSR_Clear_EIP = '1' then
      ex_msr_cmb(MSR_EIP_POS) <= '0';
    end if;

    -- load FSL error
    if (EX_FSL_Control_Error = '1') then
      ex_MSR_cmb(MSR_FSL_POS) <= '1';
    end if;

    -- clear UM and VM bits
    -- restore UM and VM when Exception, HW Break or Interrupt ends
    if C_USE_MMU >= C_MMU_USERMODE then
      if EX_MSR_Clear_VM_UM = '1' then
        ex_msr_cmb(MSR_UM_POS) <= '0';
      end if;
      if EX_MSR_Clear_EIP = '1' or
         EX_MSR_Clear_BIP = '1' or
         EX_MSR_Set_IE    = '1' then
        ex_msr_cmb(MSR_UM_POS) <= ex_MSR_i(MSR_UMS_POS);
      end if;
    end if;
    if C_USE_MMU >= C_MMU_PROTECT then
      if EX_MSR_Clear_VM_UM = '1' then
        ex_msr_cmb(MSR_VM_POS) <= '0';
      end if;
      if EX_MSR_Clear_EIP = '1' or
         EX_MSR_Clear_BIP = '1' or
         EX_MSR_Set_IE    = '1' then
        ex_msr_cmb(MSR_VM_POS) <= ex_MSR_i(MSR_VMS_POS);
      end if;
    end if;
  end process ex_msr_handler;

  ex_msr_FF: process (clk)
  begin  -- process ex_msr_handler
    if clk'event and clk = '1' then  -- rising clock edge
      if Rst = '1' then
        ex_msr_i <= C_RESET_MSR;
      elsif restore_wb_msr_to_ex = '1' then
        ex_msr_i <= wb_MSR_cmb;
      elsif ex_piperun then
        ex_msr_i <= ex_MSR_cmb;
      end if;
    end if;
  end process ex_msr_FF;

  of_msr_FF: process (clk)
  begin  -- process of_msr_handler
    if clk'event and clk = '1' then  -- rising clock edge
      if Rst = '1' then
        of_msr_i <= C_RESET_MSR;
      elsif restore_wb_msr_to_ex = '1' then
        of_msr_i <= wb_MSR_cmb;
      else
        if of_piperun then
          of_msr_i <= ex_MSR_cmb;
        elsif EX_MSR_Set_SW_BIP = '1' then
          of_msr_i(MSR_BIP_POS) <= '1';
        end if;
      end if;
    end if;
  end process of_msr_FF;

  -----------------------------------------------------------------------------
  -- Assign to external ports.
  -- Add Carry Copy bit
  -----------------------------------------------------------------------------
  Assign_External : process(of_MSR_i, ex_MSR_i, mem_MSR_i, wb_MSR_i)
  begin  -- process Assign_External
    -- default
    OF_MSR  <= (others => '0');
    EX_MSR  <= (others => '0');
    MEM_MSR <= (others => '0');
    WB_MSR  <= (others => '0');

    -- Compulsory MSR bits
    OF_MSR(MSR_BIP_POS to MSR_IE_POS)  <= of_MSR_i(MSR_BIP_POS to MSR_IE_POS);
    EX_MSR(MSR_BIP_POS to MSR_IE_POS)  <= ex_MSR_i(MSR_BIP_POS to MSR_IE_POS);
    MEM_MSR(MSR_BIP_POS to MSR_IE_POS) <= mem_MSR_i(MSR_BIP_POS to MSR_IE_POS);
    WB_MSR(MSR_BIP_POS to MSR_IE_POS)  <= wb_MSR_i(MSR_BIP_POS to MSR_IE_POS);
    
    -- Optional MSR bits
    if C_USE_DIV then
      EX_MSR(MSR_DZ_POS)  <= ex_MSR_i(MSR_DZ_POS);
      MEM_MSR(MSR_DZ_POS) <= mem_MSR_i(MSR_DZ_POS);
      WB_MSR(MSR_DZ_POS)  <= wb_MSR_i(MSR_DZ_POS);   
    end if;
    
    if C_USE_EXCEPTIONS then
      OF_MSR(MSR_EIP_POS to MSR_EE_POS)  <= of_MSR_i(MSR_EIP_POS to MSR_EE_POS);
      EX_MSR(MSR_EIP_POS to MSR_EE_POS)  <= ex_MSR_i(MSR_EIP_POS to MSR_EE_POS);
      MEM_MSR(MSR_EIP_POS to MSR_EE_POS) <= mem_MSR_i(MSR_EIP_POS to MSR_EE_POS);
      WB_MSR(MSR_EIP_POS to MSR_EE_POS)  <= wb_MSR_i(MSR_EIP_POS to MSR_EE_POS);   
    end if;
    
    if C_USE_ICACHE then
      EX_MSR(MSR_ICE_POS)  <= ex_MSR_i(MSR_ICE_POS);
      MEM_MSR(MSR_ICE_POS) <= mem_MSR_i(MSR_ICE_POS);
      WB_MSR(MSR_ICE_POS)  <= wb_MSR_i(MSR_ICE_POS);   
    end if;
    
    if C_USE_DCACHE then
      EX_MSR(MSR_DCE_POS)  <= ex_MSR_i(MSR_DCE_POS);
      MEM_MSR(MSR_DCE_POS) <= mem_MSR_i(MSR_DCE_POS);
      WB_MSR(MSR_DCE_POS)  <= wb_MSR_i(MSR_DCE_POS);   
    end if;
    
    if C_USE_D_OPB then
      EX_MSR(MSR_BE_POS)  <= ex_MSR_i(MSR_BE_POS);
      MEM_MSR(MSR_BE_POS) <= mem_MSR_i(MSR_BE_POS);
      WB_MSR(MSR_BE_POS)  <= wb_MSR_i(MSR_BE_POS);   
    end if;

    if C_FSL_LINKS > 0 then
      EX_MSR(MSR_FSL_POS)  <= ex_MSR_i(MSR_FSL_POS);
      MEM_MSR(MSR_FSL_POS) <= mem_MSR_i(MSR_FSL_POS);
      WB_MSR(MSR_FSL_POS)  <= wb_MSR_i(MSR_FSL_POS);   
    end if;

    if C_PVR /= C_PVR_NONE then
      EX_MSR(MSR_PVR_POS)  <= '1';
      MEM_MSR(MSR_PVR_POS) <= '1';
      WB_MSR(MSR_PVR_POS)  <= '1';
    end if;

    if C_USE_MMU >= C_MMU_USERMODE then
      EX_MSR(MSR_UM_POS)   <= ex_MSR_i(MSR_UM_POS);
      MEM_MSR(MSR_UM_POS)  <= mem_MSR_i(MSR_UM_POS);
      WB_MSR(MSR_UM_POS)   <= wb_MSR_i(MSR_UM_POS);   
      EX_MSR(MSR_UMS_POS)  <= ex_MSR_i(MSR_UMS_POS);
      MEM_MSR(MSR_UMS_POS) <= mem_MSR_i(MSR_UMS_POS);
      WB_MSR(MSR_UMS_POS)  <= wb_MSR_i(MSR_UMS_POS);   
    end if;

    if C_USE_MMU >= C_MMU_PROTECT then
      EX_MSR(MSR_VM_POS)   <= ex_MSR_i(MSR_VM_POS);
      MEM_MSR(MSR_VM_POS)  <= mem_MSR_i(MSR_VM_POS);
      WB_MSR(MSR_VM_POS)   <= wb_MSR_i(MSR_VM_POS);   
      EX_MSR(MSR_VMS_POS)  <= ex_MSR_i(MSR_VMS_POS);
      MEM_MSR(MSR_VMS_POS) <= mem_MSR_i(MSR_VMS_POS);
      WB_MSR(MSR_VMS_POS)  <= wb_MSR_i(MSR_VMS_POS);   
    end if;

    -- carry copy
    EX_MSR(MSR_CC_POS)  <= ex_MSR_i(MSR_C_POS);
    MEM_MSR(MSR_CC_POS) <= mem_MSR_i(MSR_C_POS);
    WB_MSR(MSR_CC_POS)  <= wb_MSR_i(MSR_C_POS);

  end process Assign_External;

end msr_reg;