msr_reg_gti.vhd

Xilinx软核microblaze源码(VHDL)版本7.10

--SINGLE_FILE_TAG
-------------------------------------------------------------------------------
-- $Id: msr_reg_gti.vhd,v 1.1 2007/10/12 09:11:36 stefana Exp $
-------------------------------------------------------------------------------
-- MSR register entity and architecture
-------------------------------------------------------------------------------
--
-- ****************************************************************************
-- ** Copyright(C) 2001-2005 by Xilinx, Inc. All rights reserved.
-- **
-- ** This text contains proprietary, confidential information of
-- ** Xilinx, Inc. , is distributed by under license from Xilinx, Inc.,
-- ** and may be used, copied and/or disclosed only pursuant to the
-- ** terms of a valid license agreement with Xilinx, Inc.
-- **
-- ** Unmodified source code is guaranteed to place and route,
-- ** function and run at speed according to the datasheet
-- ** specification. Source code is provided "as-is", with no
-- ** obligation on the part of Xilinx to provide support.
-- **
-- ** Xilinx Hotline support of source code IP shall only include
-- ** standard level Xilinx Hotline support, and will only address
-- ** issues and questions related to the standard released Netlist
-- ** version of the core (and thus indirectly, the original core source
-- **
-- ** The Xilinx Support Hotline does not have access to source
-- ** code and therefore cannot answer specific questions related
-- ** to source HDL. The Xilinx Support Hotline will only be able
-- ** to confirm the problem in the Netlist version of the core.
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-- ** This copyright and support notice must be retained as part
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-- ****************************************************************************
--
-------------------------------------------------------------------------------
-- Filename:        msr_reg.vhd
-- Version:         v5.00a
-- Description:     MicroBlaze Machine Status Register
--                  
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:   
--              msr_reg.vhd
--
-------------------------------------------------------------------------------
-- Naming Conventions:
--      active low signals:                     "*_n"
--      clock signals:                          "clk", "*_clk"
--      reset signals:                          "rst", "*_rst", "reset"
--      generics:                               All uppercase, starting with: "C_"
--      constants:                              All uppercase, not starting with: "C_"
--      state machine next state:               "*_next_state"
--      state machine current state:            "*_curr_state"
--      pipelined signals:                      "*_d#"
--      counter signals:                        "*_cnt_*" , "*_counter_*", "*_count_*"
--      internal version of output port:        "*_i"
--      ports:                                  Names begin with uppercase
--      component instantiations:               "<ENTITY>_I#|<FUNC>" , "<ENTITY>_I"
--
-- Signals starting with IF, OF, EX, MEM, or WB indicate that they start in that
-- stage:
--
--    IF                      -- instruction fetch
--    OF                      -- operand fetch
--    EX                      -- execute
--    MEM                     -- memory
--    WB                      -- write back
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;

library microblaze_v7_10_a;
use microblaze_v7_10_a.microblaze_types.all;
use microblaze_v7_10_a.microblaze_isa.all;

entity msr_reg_gti is
  
  generic (
    C_RESET_MSR      : MSR_TYPE := (others => '0');
    C_PVR            : integer;   -- Which PVR mode None=0, Basic=1, Full=2
    C_USE_MMU        : integer;   -- Which MMU mode None=0, Usermode=1, Protect=2, Virtual=3
    C_USE_DIV        : boolean := false;
    C_USE_D_OPB      : boolean := false;
    C_FSL_LINKS      : integer := 0;
    C_USE_ICACHE     : boolean := false;
    C_USE_DCACHE     : boolean := false;
    C_USE_EXCEPTIONS : boolean := false
    );

  port (
    Clk                  : in std_logic;
    Rst                  : in std_logic;
    -- data_flow internal
    EX_Op1               : in DATA_TYPE;
    EX_Op2               : in DATA_TYPE;
    EX_ALU_Carry         : in std_logic;
    EX_Shift_Carry       : in std_logic;
    EX_FSL_Carry         : in std_logic;
    EX_FSL_Control_Error : in std_logic;
    MEM_DivideByZero     : in boolean;
    -- from decode
    OF_PipeRun           : in boolean;
    EX_PipeRun           : in boolean;
    EX_MSR_Load_ALU_C    : in std_logic;
    EX_MSR_Load_Shift_C  : in std_logic;
    EX_MSR_Load_FSL_C    : in std_logic;
    EX_MSR_Set_IE        : in std_logic;
    EX_MSR_Set_EE        : in std_logic;
    EX_MSR_Clear_EIP     : in std_logic;
    EX_MSR_Set_SW_BIP    : in std_logic;
    EX_MSR_Clear_BIP     : in std_logic;
    EX_MSR_Clear_VM_UM   : in std_logic;
    EX_MTS_MSR           : in std_logic;
    EX_MSRCLR            : in std_logic;
    EX_MSRSET            : in std_logic;
    EX_Restore_WB_MSR    : in std_logic;
    MEM_PipeRun          : in boolean;
    MEM_MSR_Load_DZ      : in std_logic;  -- not used since divbyzero flag is
                                          -- always correct
    WB_PipeRun           : in boolean;
    WB_MSR_Clear_IE      : in std_logic;
    WB_MSR_Clear_EE      : in std_logic;
    WB_MSR_Set_EIP       : in std_logic;
    WB_MSR_Set_HW_BIP    : in std_logic;

    OF_MSR     : out DATA_TYPE;
    EX_MSR     : out DATA_TYPE;
    MEM_MSR    : out DATA_TYPE;
    WB_MSR     : out DATA_TYPE);
end msr_reg_gti;

architecture msr_reg of msr_reg_gti is

  signal ex_MSR_cmb  : MSR_TYPE;
  signal mem_MSR_cmb : MSR_TYPE;
  signal wb_MSR_cmb  : MSR_TYPE;
  signal of_MSR_i    : MSR_TYPE;
  signal ex_MSR_i    : MSR_TYPE;
  signal mem_MSR_i   : MSR_TYPE;
  signal wb_MSR_i    : MSR_TYPE;

  signal restore_wb_msr_to_ex : std_logic;
  
begin  -- msr_reg
  -----------------------------------------------------------------------------
  -- WB stage
  -----------------------------------------------------------------------------
  restore_wb_msr_to_ex <= (WB_MSR_Clear_IE or WB_MSR_Set_EIP or WB_MSR_Set_HW_BIP);

  wb_msr_handler: process (WB_MSR_Clear_IE, WB_MSR_Set_EIP, WB_MSR_Set_HW_BIP,
                           mem_MSR_i, restore_wb_msr_to_ex, wb_MSR_i)
  begin  -- process wb_msr_handler
    -- default assignment
    wb_MSR_cmb <= mem_MSR_i;

    -- Exception
    if WB_MSR_Set_EIP = '1' then        -- WB_MSR_Clear_EE = '1' redundant
      wb_MSR_cmb(MSR_EIP_POS) <= '1';
      wb_MSR_cmb(MSR_EE_POS) <= '0';
    end if;
    -- HW Break
    if WB_MSR_Set_HW_BIP = '1' then
      wb_MSR_cmb(MSR_BIP_POS) <= '1';
    end if;
    -- Interrupt
    if WB_MSR_Clear_IE = '1' then
      wb_MSR_cmb(MSR_IE_POS) <= '0';
    end if;
    -- save and clear UM and VM when Exception, HW Break or Interrupt occurs
    if C_USE_MMU >= C_MMU_USERMODE then
      if restore_wb_msr_to_ex = '1' then
        wb_MSR_cmb(MSR_UMS_POS) <= wb_MSR_i(MSR_UM_POS);
        wb_MSR_cmb(MSR_UM_POS)  <= '0';
      end if;
    end if;
    if C_USE_MMU >= C_MMU_PROTECT then
      if restore_wb_msr_to_ex = '1' then
        wb_MSR_cmb(MSR_VMS_POS) <= wb_MSR_i(MSR_VM_POS);
        wb_MSR_cmb(MSR_VM_POS)  <= '0';
      end if;
    end if;
  end process wb_msr_handler;
  
  wb_msr_FF: process (clk)
  begin  -- process wb_msr_handler
    if clk'event and clk = '1' then  -- rising clock edge
      if Rst = '1' then
        wb_msr_i <= (others => '0');
      elsif wb_piperun then
        wb_msr_i <= wb_msr_cmb;
      end if;
    end if;
  end process wb_msr_FF;

  -----------------------------------------------------------------------------
  -- MEM stage
  -----------------------------------------------------------------------------
  mem_msr_handler: process(ex_MSR_i, MEM_DivideByZero)
  begin  -- process mem_msr_handler
    -- default assignment
    mem_MSR_cmb <= ex_MSR_i;

    -- WB pipeline forwarding:
    -- no need to forward the wb_MSR_i value since interrupts/breaks/exceptions
    -- all flush the pipeline and forward the WB_MSR all the way to EX_MSR

    -- MEM stage MSR side effects:
    if MEM_DivideByZero then
      mem_MSR_cmb(MSR_DZ_POS) <= '1';
    end if;
  end process mem_msr_handler; 

  mem_msr_FF: process (clk)
  begin  -- process mem_msr_handler
    if clk'event and clk = '1' then  -- rising clock edge
      if Rst = '1' then
        mem_msr_i <= (others => '0');
      elsif restore_wb_msr_to_ex = '1' then
        mem_msr_i <= wb_MSR_cmb;