pc_module_gti.vhd

Xilinx软核microblaze源码(VHDL)版本7.10

--SINGLE_FILE_TAG
-------------------------------------------------------------------------------
-- $Id: pc_module_gti.vhd,v 1.1 2007/10/12 09:11:36 stefana Exp $
-------------------------------------------------------------------------------
-- pc_module.vhd - entity/architecture pair
-------------------------------------------------------------------------------
--
-- ****************************************************************************
-- ** Copyright(C) 2001-2005 by Xilinx, Inc. All rights reserved.
-- **
-- ** This text contains proprietary, confidential information of
-- ** Xilinx, Inc. , is distributed by under license from Xilinx, Inc.,
-- ** and may be used, copied and/or disclosed only pursuant to the
-- ** terms of a valid license agreement with Xilinx, Inc. 
-- **
-- ** Unmodified source code is guaranteed to place and route, 
-- ** function and run at speed according to the datasheet
-- ** specification. Source code is provided "as-is", with no
-- ** obligation on the part of Xilinx to provide support.
-- **
-- ** Xilinx Hotline support of source code IP shall only include
-- ** standard level Xilinx Hotline support, and will only address
-- ** issues and questions related to the standard released Netlist
-- ** version of the core (and thus indirectly, the original core source
-- **
-- ** The Xilinx Support Hotline does not have access to source
-- ** code and therefore cannot answer specific questions related
-- ** to source HDL. The Xilinx Support Hotline will only be able
-- ** to confirm the problem in the Netlist version of the core.
-- **
-- ** This copyright and support notice must be retained as part
-- ** of this text at all times.
-- ****************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: pc_module.vhd
-- Version: v2.00a
-- Description: Implements the Program Counter (PC)
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:   
--              pc_module.vhd
-------------------------------------------------------------------------------
-- Author:          goran
-- History:
--   goran  2001-03-05    First Version
--   BJS    2005-03-25
-- ^^^^^^
--                        Updated for new pipeline
-- ~~~~~~
--
--
-------------------------------------------------------------------------------
-- Naming Conventions:
--      active low signals:                     "*_n"
--      clock signals:                          "clk", "*_clk"
--      reset signals:                          "rst", "*_rst", "reset"
--      generics:                               All uppercase, starting with: "C_"
--      constants:                              All uppercase, not starting with: "C_"
--      state machine next state:               "*_next_state"
--      state machine current state:            "*_curr_state"
--      pipelined signals:                      "*_d#"
--      counter signals:                        "*_cnt_*" , "*_counter_*", "*_count_*"
--      internal version of output port:        "*_i"
--      ports:                                  Names begin with uppercase
--      component instantiations:               "<ENTITY_>I_<#|FUNC>" , "ENTITY>_I#" 
--
-- Signals starting with IF, OF, EX, MEM, or WB indicate that they start in that
-- stage:
--
--    IF                      -- instruction fetch
--    OF                      -- operand fetch
--    EX                      -- execute
--    MEM                     -- memory
--    WB                      -- write back
-------------------------------------------------------------------------------

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;

library unisim;
use unisim.vcomponents.all;

--------------------------------------------------------------------------
-- Include MicroBlaze package for data types
--------------------------------------------------------------------------
library Microblaze_v7_10_a;
use Microblaze_v7_10_a.MicroBlaze_ISA.all;
use Microblaze_v7_10_a.MicroBlaze_Types.all;

-------------------------------------------------------------------------------
-- Port Declaration
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Definition of Generics:
--
--    C_TARGET                -- Device family
--    C_U_SET                 -- Name of unit
--
-- Definition of Ports:
--
--    Clk                     -- Clock
--    Reset                   -- internal reset
--
--    IF_Valid_Fetch          -- Instruction Fetch valid strobe
--    OF_PipeRun              -- Move the operand fetch stage
--
--    IF_PC_Incr              -- Program counter increment strobe
--
--    EX_Jump                 -- Branch to a new PC
--    EX_ALU_Result           -- Output from ALU
--
--    IF_PC_Write             -- Porgram counter write strobe
--    IF_PC_Buffer_Addr       -- PC buffer address
--
--    OF_PC                   -- Operand Fetch stage program counter
--    EX_PC                   -- Program counter in execute stage
--    IB_Addr                 -- Instruction bus address
--
-------------------------------------------------------------------------------
entity PC_Module_gti is
  generic (

    C_TARGET                : TARGET_FAMILY_TYPE;

    -- pragma xilinx_rtl_off
    C_U_SET                 : string                  := "dataflow"
    -- pragma xilinx_rtl_on
  );
  port (
    Clk               : in  std_logic;
    Reset             : in  std_logic;
 
    IF_Valid_Fetch    : in  boolean;
    OF_PipeRun        : in  boolean;
    EX_PipeRun        : in  boolean;
    MEM_PipeRun       : in  boolean;

    IF_PC_Incr        : in  boolean;

    EX_Jump           : in  boolean;
    EX_ALU_Result     : in  DATA_TYPE;

    IF_PC_Write       : in  boolean;
    IB_Buffer_En      : in  slv_0to3;
    OF_Buffer_Sel     : in  slv_0to1;

    OF_PC             : out DATA_TYPE;
    EX_PC             : out DATA_TYPE;
    WB_PC             : out DATA_TYPE;
    IB_Addr           : out DATA_TYPE
  );

end entity PC_Module_gti;

--------------------------------------------------------------------------
-- Architecture section
--------------------------------------------------------------------------

architecture IMP of PC_Module_gti is

  component mux4 is
    generic (
      D_Size : natural);
    port (
      A   : in  std_logic_vector(0 to D_Size-1);
      B   : in  std_logic_vector(0 to D_Size-1);
      C   : in  std_logic_vector(0 to D_Size-1);
      D   : in  std_logic_vector(0 to D_Size-1);
      Sel : in  std_logic_vector(0 to 1);
      Res : out std_logic_vector(0 to D_Size-1));
  end component mux4;

  constant WORD_BIT       : integer           :=
    DATA_TYPE'right - 2;

  constant PC_RESET_VALUE : DATA_TYPE         :=
    std_logic_vector(signed(PC_START_ADDR)-4);

  signal ex_pc_piperun    : boolean;

  signal new_pc           : DATA_TYPE;
  signal new_pc_incr      : DATA_TYPE;
  signal if_pc            : DATA_TYPE;
  signal of_pc_i          : DATA_TYPE;
  signal ex_pc_i          : DATA_TYPE;
  signal mem_pc_i         : DATA_TYPE;
  signal wb_pc_i          : DATA_TYPE;

  type   PC_BUFFER_TYPE is array(0 to 3) of DATA_TYPE;
  signal PC_Buffer : PC_BUFFER_TYPE := (others => (others => '0'));
  
begin

  ex_pc_piperun <= OF_PipeRun;

  ----------------------------------------
  -- Calculate the new program counter
  -- Either increment to the next instruction word, or jump to a new PC
  ----------------------------------------

  Using_RTL : if (C_TARGET = RTL) generate
    signal increment : DATA_TYPE;
  begin
    ----------------------------------------
    -- Increment_PROCESS
    -- Amount to increment PC by
    -- (FPGA: Creates mask of bits in the PC to increment)
    -- Increments the word bit
    ----------------------------------------
    Increment_PROCESS : process (IF_PC_Incr) is
    begin
      increment             <= (others => '0');
      if IF_PC_Incr then
        increment(WORD_BIT) <= '1';
      end if;
    end process Increment_PROCESS;

    new_pc_incr <= std_logic_vector(unsigned(if_pc) + unsigned(increment));
  end generate Using_RTL;

  Using_FPGA : if (C_TARGET /= RTL) generate
    signal if_pc_carry : std_logic_vector(0 to 30);
  begin
    if_pc_carry(30) <= '1' when IF_PC_Incr else '0';

    Incr_PC : for I in 29 downto 0 generate
    begin  -- generate Incr_PC

      MUXCY_I : MUXCY_L
        port map (
          DI => '0',
          CI => if_pc_carry(I+1),
          S  => if_pc(I),
          LO => if_pc_carry(I));

      XOR_I : XORCY
        port map (
          LI => if_pc(I),
          CI => if_pc_carry(I+1),
          O  => new_pc_incr(I));

    end generate Incr_PC;

    new_pc_incr(30 to 31) <= if_pc(30 to 31);
  end generate Using_FPGA;

  new_pc <= EX_ALU_Result when EX_Jump else new_pc_incr;

  ----------------------------------------
  -- IF_PC_DFF
  -- Instruction fetch stage program counter
  ----------------------------------------
  IF_PC_DFF: process (Clk) is
  begin
    if Clk'event and Clk = '1' then   -- rising clock edge
      if Reset = '1' then
        if_pc <= PC_RESET_VALUE;
      elsif IF_PC_Write then
        if_pc <= new_pc;
      end if;
    end if;
  end process IF_PC_DFF;

  ----------------------------------------
  -- PC_Buffer_DFF 
  -- OF stage program counter buffer
  ----------------------------------------
  The_IBuffers : for I in PC_BUFFER_TYPE'range generate
    ibuffer_DFF : process (Clk) is
    begin  -- process ibuffer_DFF
      if Clk'event and Clk = '1' then   -- rising clock edge
        if Reset = '1' then                   -- synchronous reset (active true)
          PC_Buffer(I) <= (others => '0');
        else
          if ((IB_Buffer_En(I) = '1') and IF_Valid_Fetch) then
            PC_Buffer(I) <= if_pc;
          end if;
        end if;
      end if;
    end process ibuffer_DFF;
  end generate The_IBuffers;

  -----------------------------------------------------------------------------
  -- The PC mux located in OF stage
  -----------------------------------------------------------------------------
  pc_mux4_I1 : mux4
    generic map (
      D_Size => 32)                     -- [natural]
    port map (
      A      => PC_Buffer(0),           -- [in  std_logic_vector(0 to D_Size-1)]
      B      => PC_Buffer(1),           -- [in  std_logic_vector(0 to D_Size-1)]
      C      => PC_Buffer(2),           -- [in  std_logic_vector(0 to D_Size-1)]
      D      => PC_Buffer(3),           -- [in  std_logic_vector(0 to D_Size-1)]
      Sel    => OF_Buffer_Sel,          -- [in  std_logic_vector(0 to 1)]
      Res    => of_pc_i);               -- [out std_logic_vector(0 to D_Size-1)]

  ----------------------------------------
  -- EX_PC_DFF
  -- Execute stage program counter
  ----------------------------------------
  EX_PC_DFF: process (Clk) is
  begin
    if Clk'event and Clk = '1' then   -- rising clock edge
      if Reset = '1' then
        ex_PC_I <= (others => '0');
      elsif ex_pc_piperun then
        ex_PC_I <= of_pc_i;
      end if;
    end if;
  end process EX_PC_DFF;

  OF_PC   <= of_pc_i;
  IB_Addr <= new_pc;

  EX_PC <= ex_pc_i;
  
  -----------------------------------------------------------------------------
  -- MEM PC
  -----------------------------------------------------------------------------
  MEM_PC_DFF: process (Clk) is
  begin  -- process MEM_PC_DFF
    if Clk'event and Clk = '1' then     -- rising clock edge
      if Reset = '1' then               -- synchronous reset (active high)
        mem_PC_I <= (others => '0');
      elsif (EX_PipeRun) then        
        mem_PC_I <= ex_PC_I;
      end if;
    end if;
  end process MEM_PC_DFF;

  -----------------------------------------------------------------------------
  -- WB PC
  -----------------------------------------------------------------------------
  WB_PC_DFF: process (Clk) is
  begin  -- process WB_PC_DFF
    if Clk'event and Clk = '1' then     -- rising clock edge
      if Reset = '1' then               -- synchronous reset (active high)
        wb_PC_I <= (others => '0');
      elsif (MEM_PipeRun) then        
        wb_PC_I <= mem_PC_I;
      end if;
    end if;
  end process WB_PC_DFF;

  WB_PC <= wb_PC_I;
  
end architecture IMP;