dcache.vhd

Xilinx软核microblaze源码(VHDL)版本7.10

  Using_FPGA_FSL_2 : if C_TARGET /= RTL generate
    signal combined_DReady_n : std_logic;
  begin
    
    Using_8word_lines : if (C_CACHELINE_SIZE = 8) generate
      signal temp_Data_Addr   : std_logic_vector(0 to CACHELINE_BITS-1);
    begin
      temp_Data_Addr <= Data_Addr_1(30-CACHELINE_BITS to 29);

      Using_8Line_4LUT : if ( not C_LUT6_OPTIMIZED ) generate
        signal addr_dec          : std_logic_vector(0 to 7);
        signal valid_check_sel   : std_logic_vector(0 to 3);
        signal valid_check_carry : std_logic_vector(0 to 4);
      begin
        Gen_Addr_Decoder : process (temp_Data_Addr) is
        begin  -- process Gen_Addr_Decoder
          addr_dec                                       <= (others => '0');
          addr_dec(to_integer(unsigned(temp_Data_Addr))) <= '1';
        end process Gen_Addr_Decoder;
  
        valid_check_carry(4) <= tag_ok;
        
        valid_check_cacheline : for I in 3 downto 0 generate
        begin
          -- Pass carry value when no addr_dec is set
          -- Force a zero when one addr_dec is set and the mem_tag_bits is not set
          valid_check_sel(I) <=
                              -- Passing when no addr_dec is set
                              '1' when (addr_dec(2*I+1)='0' and (addr_dec(2*I)='0')) else
                              -- Passing if the corresponding mem_tag_bit is set
                              '1' when (addr_dec(2*I+1) = '1') and (tag_bits(2*I+1) = '1') else
                              '1' when (addr_dec(2*I) = '1') and (tag_bits(2*I) = '1') else
                              '0';
  
          valid_check_carry_and_I : carry_and
            generic map (C_TARGET => C_TARGET)              -- [TARGET_FAMILY_TYPE]
            port map (Carry_IN  => valid_check_carry(I+1),  -- [in  std_logic]
                      A         => valid_check_sel(I),      -- [in  std_logic]
                      Carry_OUT => valid_check_carry(I));   -- [out std_logic]
  
        end generate valid_check_cacheline;
  
        Word_Is_Valid <= valid_check_carry(0);
      end generate Using_8Line_4LUT;
      
      Using_8Line_6LUT : if ( C_LUT6_OPTIMIZED ) generate
        signal valid_check_sel   : std_logic_vector(0 to 2);
        signal valid_check_carry : std_logic_vector(0 to 3);
      begin
  
        valid_check_carry(3) <= tag_ok;
        
        valid_check_sel(0) <= tag_bits(0) when ( temp_Data_Addr = "000" ) else
                              tag_bits(1) when ( temp_Data_Addr = "001" ) else
                              tag_bits(2) when ( temp_Data_Addr = "010" ) else
                              '1';                                             -- Bypass
        
        valid_check_sel(1) <= tag_bits(3) when ( temp_Data_Addr = "011" ) else
                              tag_bits(4) when ( temp_Data_Addr = "100" ) else
                              tag_bits(5) when ( temp_Data_Addr = "101" ) else
                              '1';                                             -- Bypass
        
        valid_check_sel(2) <= tag_bits(6) when ( temp_Data_Addr = "110" ) else
                              tag_bits(7) when ( temp_Data_Addr = "111" ) else
                              '1';                                             -- Bypass
        
        valid_check_cacheline : for I in 2 downto 0 generate
        begin
  
          valid_check_carry_and_I : carry_and
            generic map (C_TARGET => C_TARGET)              -- [TARGET_FAMILY_TYPE]
            port map (Carry_IN  => valid_check_carry(I+1),  -- [in  std_logic]
                      A         => valid_check_sel(I),      -- [in  std_logic]
                      Carry_OUT => valid_check_carry(I));   -- [out std_logic]
  
        end generate valid_check_cacheline;
  
        Word_Is_Valid <= valid_check_carry(0);
      end generate Using_8Line_6LUT;
    end generate Using_8word_lines;

    Using_4word_lines : if (C_CACHELINE_SIZE = 4) generate
    begin
    
      Using_4LUT : if ( not C_LUT6_OPTIMIZED ) generate
        signal sel1  : std_logic;
        signal sel2  : std_logic;
        signal carry : std_logic;
      begin
        -- Data_Addr_1(28 to 29) = "11" <=> tag_bits(3)
        -- Data_Addr_1(28 to 29) = "10" <=> tag_bits(2)
        Sel1 <= not(Data_Addr_1(28)) or
                ((Data_Addr_1(29) and tag_bits(3)) or
                 (not(Data_Addr_1(29)) and tag_bits(2)));
  
        Word_Valid_MUXCY_1 : MUXCY_L
          port map (
            DI => '0',                        -- [in  std_logic]
            CI => tag_ok,
            S  => Sel1,                       -- [in  std_logic]
            LO => carry);                     -- [out std_logic]
  
        -- Data_Addr_1(28 to 29) = "01" <=> tag_bits(1)
        -- Data_Addr_1(28 to 29) = "00" <=> tag_bits(0)
        Sel2 <= Data_Addr_1(28) or
                ((Data_Addr_1(29) and tag_bits(1)) or
                 (not(Data_Addr_1(29)) and tag_bits(0)));
  
        Word_Valid_MUXCY_2 : MUXCY_L
          port map (
            DI => '0',                        -- [in  std_logic]
            CI => carry,
            S  => Sel2,                       -- [in  std_logic]
            LO => word_is_valid);             -- [out std_logic]
  
      end generate Using_4LUT;
      
      Using_6LUT : if ( C_LUT6_OPTIMIZED ) generate
        signal sel   : std_logic;
      begin
        -- Data_Addr_1(28 to 29) = "11" <=> tag_bits(3)
        -- Data_Addr_1(28 to 29) = "10" <=> tag_bits(2)
        -- Data_Addr_1(28 to 29) = "01" <=> tag_bits(1)
        -- Data_Addr_1(28 to 29) = "00" <=> tag_bits(0)
        Sel  <= tag_bits(3) when (Data_Addr_1(28 to 29) = "11") else 
                tag_bits(2) when (Data_Addr_1(28 to 29) = "10") else 
                tag_bits(1) when (Data_Addr_1(28 to 29) = "01") else 
                tag_bits(0) when (Data_Addr_1(28 to 29) = "00") else 
                '0';
        
        Lut6_Word_Valid_MUXCY : MUXCY_L
          port map (
            DI => '0',                        -- [in  std_logic]
            CI => tag_ok,
            S  => Sel,                        -- [in  std_logic]
            LO => word_is_valid);             -- [out std_logic]
  
      end generate Using_6LUT;

    end generate Using_4word_lines;

--    Cache_Hit <= (word_is_valid and Read_Strobe)
--                 or
--                 Write_Done;
--    Cache_Hit <= (valid_req and Tag_ok and Word_Is_Valid and Read_Strobe and
--                 (Dcache_Enabled_1 or (valid_cache_hit and not Dcache_Enabled_1))) or
--                 Write_Done;

    Use_XX_Accesses_Hit : if (C_DCACHE_ALWAYS_USED /= 0) generate
      dcache_data_strobe_sel2_carry_or : carry_or
        generic map (C_TARGET => C_TARGET)             -- [TARGET_FAMILY_TYPE]
        port map (Carry_IN  => Word_Is_Valid,  -- [in  std_logic]
                  A         => xx_valid_data,          -- [in  std_logic]
                  Carry_OUT => Word_Is_Valid_i);  -- [out std_logic]
      
    end generate Use_XX_Accesses_Hit;

    No_XX_Accesses2: if (C_DCACHE_ALWAYS_USED = 0) generate
      Word_Is_Valid_i <= Word_Is_Valid;
    end generate No_XX_Accesses2;
    
    
    Cache_hit_MUXCY : MUXCY_L
      port map (
        DI => Write_Done,               -- [in  std_logic]
        CI => Word_Is_Valid_i,            -- [in  std_logic]
        S  => Valid_Read_Access,        -- [in  std_logic]
        LO => Cache_Hit);               -- [out std_logic]

    combined_DReady_n <= not Combined_Dready;

    DReady_MUXCY : MUXCY_L
      port map (
        DI => '1',                      -- [in  std_logic]
        CI => Cache_Hit,                -- [in  std_logic]
        S  => combined_DReady_n,        -- [in  std_logic]
        LO => DReady_I);                -- [out std_logic]

  end generate Using_FPGA_FSL_2;

  Using_RTL_FSL_2 : if C_TARGET = RTL generate
    Word_Is_Valid_Gen : process (Data_Addr, tag_ok, tag_bits)
      variable temp_Data_Addr : std_logic_vector(0 to 1);
    begin  -- process Word_Is_Valid_Gen
      temp_Data_Addr := Data_Addr(28 to 29);
      case temp_Data_Addr is
        when "00"   => word_is_valid <= tag_bits(0) and tag_ok;
        when "01"   => word_is_valid <= tag_bits(1) and tag_ok;
        when "10"   => word_is_valid <= tag_bits(2) and tag_ok;
        when "11"   => word_is_valid <= tag_bits(3) and tag_ok;
        when others => null;
      end case;
    end process Word_Is_Valid_Gen;

    Cache_Hit <= (Valid_Read_Access and word_is_valid) or
                 ((not Valid_Read_Access) and word_is_valid);
    
    DReady_I <= Combined_Dready or Cache_Hit;

  end generate Using_RTL_FSL_2;

  Read_Strobe_DFF : process (Clk) is
  begin  -- process Read_Strobe_DFF
    if Clk'event and Clk = '1' then     -- rising clock edge
      if Reset then                     -- synchronous reset (active true)
        Read_Strobe_1 <= '0';
      else
        Read_Strobe_1 <= Read_Strobe;
      end if;
    end if;
  end process Read_Strobe_DFF;
  
--  Valid_Read_Access <= Read_Strobe_1 and (Dcache_Enabled_1 or (valid_cache_hit and not Dcache_Enabled_1));
  Valid_Read_Access <= Read_Strobe_1 and valid_cache_hit;

  ---------------------------------------------------------------------------
  -- Writing to cache can only take place if we have a tag hit, write misses
  -- will not update the cache.
  ---------------------------------------------------------------------------
  write_cachehit <= Write_Done and tag_ok;

  DReady <= DReady_I;

  Fsl_Write_Hold_Handle : process (Clk) is
  begin  -- process Fsl_Write_Hold_Handle
    if Clk'event and Clk = '1' then     -- rising clock edge
      if Reset then                     -- synchronous reset (active high)
        FSL_Write_Hold <= '0';
      else
        if (FSL_Write_Reg_i and DCACHE_FSL_OUT_Full) = '1' then
          FSL_Write_Hold <= '1';
        else
          if (FSL_Write_Hold and not DCACHE_FSL_OUT_Full) = '1' then
            FSL_Write_Hold <= '0';
          end if;
        end if;
      end if;
    end if;
  end process Fsl_Write_Hold_Handle;
  
  FSL_Write_Reg_i <= (Valid_Req_1st_Cycle_XX and (not Tag_ok or Write_Strobe_i)) or (Non_Blocked_Write);
--  FSL_Write_Reg_i <= (Valid_req_1st_cycle and not Tag_ok) or (Valid_Req_1st_Cycle_XX and Write_Strobe_i)) or (Non_Blocked_Write);

  -----------------------------------------------------------------------------
  -- Rewrite of
  -- DCACHE_FSL_OUT_Write <= (FSL_Write_Reg_i or FSL_Write_Hold) and not DCACHE_FSL_OUT_Full;
  -- in order to make sure that "Tag_Ok" only to pass 1 LUT
  -----------------------------------------------------------------------------

  fsl_write_reg_slow <= ((Valid_req_1st_cycle and Write_Strobe_i) or Non_Blocked_Write or FSL_Write_Hold) and not DCACHE_FSL_OUT_Full;

  -- Only 4 inputs to this equation, maybe need a rewrite for 6LUT architectures
  DCACHE_FSL_OUT_Write_i <= (Valid_Req_1st_Cycle_XX and not Tag_Ok and not DCACHE_FSL_OUT_Full) or fsl_write_reg_slow;
  DCACHE_FSL_OUT_Write   <= DCACHE_FSL_OUT_Write_i;

  DCACHE_FSL_OUT_Data <= FSL_Addr when Address_Written = '0' else FSL_Data;

  FSL_Addr(0 to 29) <= Data_Addr_1(0 to 29);

  Handle_Byte_Halfword_Access : process (Doublet, byte, Data_Addr_1) is
  begin  -- process Handle_Byte_Halfword_Access
    if (byte) then
      FSL_Addr(30 to 31) <= Data_Addr_1(30 to 31);
    elsif (Doublet) then
      FSL_Addr(30) <= Data_Addr_1(30);
      FSL_Addr(31) <= '1';
    else
      FSL_Addr(30 to 31) <= "00";
    end if;
  end process Handle_Byte_Halfword_Access;

  FSL_Data <= Data_Write;

  Handle_Control_Bit : process (Write_Strobe_i, Address_Written, Byte) is
  begin  -- process Handle_Control_Bit
    if (Write_Strobe_i = '1') then
      if Address_Written = '0' then
        DCACHE_FSL_OUT_Control <= '1';    -- Write request
      else
        if (Byte) then
          DCACHE_FSL_OUT_Control <= '1';  -- Byte Access
        else
          DCACHE_FSL_OUT_Control <= '0';  -- Word or Halfword
        end if;
      end if;
    else
      DCACHE_FSL_OUT_Control <= '0';      -- Read request
    end if;
  end process Handle_Control_Bit;


  ---------------------------------------------------------------------------