dcache.vhd

Xilinx软核microblaze源码(VHDL)版本7.10

-------------------------------------------------------------------------------
-- $Id: dcache.vhd,v 1.3 2007/12/21 12:50:51 stefana Exp $
-------------------------------------------------------------------------------
-- dcache.vhd
-------------------------------------------------------------------------------
--
--                  ****************************
--                  ** Copyright Xilinx, Inc. **
--                  ** All rights reserved.   **
--                  ****************************
--
-------------------------------------------------------------------------------
-- Filename:        dcache.vhd
--
-- Description:     
--                  
-- VHDL-Standard:   VHDL'93
-------------------------------------------------------------------------------
-- Structure:   
--              dcache.vhd
--
-------------------------------------------------------------------------------
-- Author:          goran
-- Revision:        $Revision: 1.3 $
-- Date:            $Date: 2007/12/21 12:50:51 $
--
-- History:
--   goran  2002-06-17    First Version
--
-------------------------------------------------------------------------------
-- Naming Conventions:
--      active low signals:                     "*_n"
--      clock signals:                          "clk", "clk_div#", "clk_#x" 
--      reset signals:                          "rst", "rst_n" 
--      generics:                               "C_*" 
--      user defined types:                     "*_TYPE" 
--      state machine next state:               "*_ns" 
--      state machine current state:            "*_cs" 
--      combinatorial signals:                  "*_com" 
--      pipelined or register delay signals:    "*_d#" 
--      counter signals:                        "*cnt*"
--      clock enable signals:                   "*_ce" 
--      internal version of output port         "*_i"
--      device pins:                            "*_pin" 
--      ports:                                  - Names begin with Uppercase 
--      processes:                              "*_PROCESS" 
--      component instantiations:               "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

library Microblaze_v7_10_a;
use Microblaze_v7_10_a.MicroBlaze_Types.all;

-------------------------------------------------------------------------------
-- Port declarations
-------------------------------------------------------------------------------

entity DCache is
  generic (
    C_D_EXT              : boolean                   := true;
    C_OPB_WIDTH          : natural                   := 32;
    C_DATA_SIZE          : natural                   := 32;
    C_TARGET             : TARGET_FAMILY_TYPE;
    C_DCACHE_BASEADDR    : std_logic_vector(0 to 31) := X"00000000";
    C_DCACHE_HIGHADDR    : std_logic_vector(0 to 31) := X"3FFFFFFF";
    C_CACHELINE_SIZE     : natural                   := 4;
    C_ALLOW_DCACHE_WR    : integer                   := 0;
    C_ADDR_TAG_BITS      : natural                   := 9;
    C_CACHE_BYTE_SIZE    : natural                   := 8*1024;
    C_DCACHE_ALWAYS_USED : integer                   := 0
    );
  port (
    -- global signals
    Clk   : in std_logic;
    Reset : in boolean;

    -- Local Bus signals
    Data_Addr           : in  std_logic_vector(0 to C_DATA_SIZE-1);
    D_AS                : in  std_logic;
    Data_Write          : in  std_logic_vector(0 to 31);
    Data_Read           : out std_logic_vector(0 to 31);
    DReady              : out std_logic;
    Read_Strobe         : in  std_logic;
    Write_Strobe        : in  std_logic;
    Byte_Enable         : in  std_logic_vector(0 to 3);
    Read_Strobe_No_Dbg  : in  std_logic;
    Write_Strobe_No_Dbg : in  std_logic;
    Byte                : in  boolean;
    Doublet             : in  boolean;

    -- Existing Extern Data Bus bus signals
    DExt_Data_Read : in std_logic_vector(0 to C_DATA_SIZE-1);
    DExt_DReady    : in std_logic;

    -- Combine DLMB and DExt ready signal
    Combined_Dready : in std_logic;

    -- Control signals
    DCache_Enabled : in boolean;
    Op1            : in std_logic_vector(0 to C_OPB_WIDTH-1);
    Op2            : in std_logic_vector(0 to C_OPB_WIDTH-1);
    Write_DCache   : in boolean;

    -- Trace signals
    Trace_Cache_Req : out std_logic;
    Trace_Cache_Hit : out std_logic;

    -- Abort external data bus access since it was a valid dcache request
    Valid_Dcache_Access : out std_logic;

    -- Set when read access is not in progress
    DCache_Read_Idle    : out boolean;

    -- FSL signals
    DCACHE_FSL_IN_Clk     : out std_logic;
    DCACHE_FSL_IN_Read    : out std_logic;
    DCACHE_FSL_IN_Data    : in  std_logic_vector(0 to 31);
    DCACHE_FSL_IN_Control : in  std_logic;
    DCACHE_FSL_IN_Exists  : in  std_logic;

    DCACHE_FSL_OUT_Clk     : out std_logic;
    DCACHE_FSL_OUT_Write   : out std_logic;
    DCACHE_FSL_OUT_Data    : out std_logic_vector(0 to 31);
    DCACHE_FSL_OUT_Control : out std_logic;
    DCACHE_FSL_OUT_Full    : in  std_logic
    );

end entity DCache;

-------------------------------------------------------------------------------
-- Architecture section
-------------------------------------------------------------------------------

library unisim;
use unisim.vcomponents.all;

architecture IMP of DCache is

  constant C_LUT6_OPTIMIZED      : boolean := ( C_TARGET = VIRTEX5 );
  
  component comparator is
    generic (
      C_TARGET    : TARGET_FAMILY_TYPE;
      C_IS_FIRST  : boolean;
      C_SIZE      : natural);
    port (
      Carry_IN  : in  std_logic;
      DI        : in std_logic;
      A         : in  std_logic_vector(0 to C_SIZE-1);
      B         : in  std_logic_vector(0 to C_SIZE-1);
      Carry_OUT : out std_logic);
  end component comparator;

  component carry_and is
    generic (
      C_TARGET : TARGET_FAMILY_TYPE);
    port (
      Carry_IN  : in  std_logic;
      A         : in  std_logic;
      Carry_OUT : out std_logic);
  end component carry_and;

  component carry_or is
    generic (
      C_TARGET : TARGET_FAMILY_TYPE);
    port (
      Carry_IN  : in  std_logic;
      A         : in  std_logic;
      Carry_OUT : out std_logic);
  end component carry_or;

  component RAM_Module is
    generic (
      C_TARGET     : TARGET_FAMILY_TYPE;
      C_DATA_WIDTH : natural range 1 to 36;
      C_ADDR_WIDTH : natural range 1 to 14;
      C_FORCE_BRAM : boolean);
    port (
      -- PORT A
      CLKA      : in  std_logic;
      WEA       : in  std_logic_vector(0 to 3);  -- Assume byte write handling
      ENA       : in  std_logic;
      ADDRA     : in  std_logic_vector(0 to C_ADDR_WIDTH-1);
      DATA_INA  : in  std_logic_vector(0 to C_DATA_WIDTH-1);
      DATA_OUTA : out std_logic_vector(0 to C_DATA_WIDTH-1);
      -- PORT B
      CLKB      : in  std_logic;
      WEB       : in  std_logic_vector(0 to 3);  -- Assume byte write handling
      ENB       : in  std_logic;
      ADDRB     : in  std_logic_vector(0 to C_ADDR_WIDTH-1);
      DATA_INB  : in  std_logic_vector(0 to C_DATA_WIDTH-1);
      DATA_OUTB : out std_logic_vector(0 to C_DATA_WIDTH-1));
  end component RAM_Module;

  function log2(x : natural) return integer is
    variable i : integer := 0;
  begin
    if x = 0 then return 0;
    else
      while 2**i < x loop
        i := i+1;
      end loop;
      return i;
    end if;
  end function log2;

  function Addr_Bits (x, y : std_logic_vector(0 to 31)) return integer is
    variable addr_nor : std_logic_vector(0 to 31);
  begin
    addr_nor := x xor y;
    for i in 0 to 31 loop
      if addr_nor(i) = '1' then return i;
      end if;
    end loop;
    return(32);
  end function Addr_Bits;

  constant C_VALID_ADDR_BITS : integer := Addr_Bits(C_DCACHE_HIGHADDR, C_DCACHE_BASEADDR);

  function calc_addr_tag_bits return natural is
    variable temp : integer;
  begin  -- function calc_addr_tag_bits
    if (C_ADDR_TAG_BITS /= 0) then
      return C_ADDR_TAG_BITS;
    else
      -- The number of needed address tag bits is the full 32 bit address
      -- minus the number of bits of the cache size since it's direct mapped and
      -- minus the number of bits outside the cacheable address range
      temp := 32 - log2(C_CACHE_BYTE_SIZE) - C_VALID_ADDR_BITS;
      if (temp > 0) then
        return temp;
      elsif (temp = 0) then  -- Enforce a tag size of at least 1, otherwise the code breaks
        return 1;
      else
        assert false report "To large data cache for the selected cacheable address range" severity failure;
        return 1;
      end if;
    end if;
  end function calc_addr_tag_bits;

  -----------------------------------------------------------------------------
  -- Constant and types
  -----------------------------------------------------------------------------
  constant NO_ADDR_TAG_BITS      : natural := calc_addr_tag_bits;
  constant Nr_Bits_In_Cache_Line : natural := log2(C_CACHE_BYTE_SIZE/4);

  constant Tag_Word_Size    : natural := C_CACHELINE_SIZE + 1 + NO_ADDR_TAG_BITS;

  constant CACHELINE_BITS : natural := log2(C_CACHELINE_SIZE);

  constant Nr_Of_Tag_Words : natural := (C_CACHE_BYTE_SIZE)/(C_CACHELINE_SIZE*4);
  constant Tag_Addr_Size   : natural := log2(Nr_Of_Tag_Words);
  subtype  TAG_ADDR_TYPE is std_logic_vector(0 to Tag_Addr_Size-1);
  subtype  TAG_WORD_TYPE is std_logic_vector(0 to Tag_Word_Size-1);

  constant Nr_Of_Data_Words : natural := (C_CACHE_BYTE_SIZE/4);
  constant Data_Addr_Size   : natural := log2(Nr_Of_Data_Words);
  subtype  DATA_ADDR_TYPE is std_logic_vector(0 to Data_Addr_Size-1);
  subtype  DATA_WORD_TYPE is std_logic_vector(0 to 31);

  -- Always use BRAM for tag if data RAM is >= 2048 bits
  constant Tag_Force_BRAM  : boolean := Data_Addr_Size >= 9;

  -- C_CACHE_BYTE_SIZE (in bytes) * 8 = cache size in bits
  -- 2048 (bytes/BRAM) * 8 (bits/byte) = 16384 bits/BRAM = 16 * 1024 bits/BRAM
  -- Round correctly: + 16*1024 - 1
  constant nr_of_data_brams : natural := (C_CACHE_BYTE_SIZE*8 + 16*1024 - 1) / (16*1024);

-------------------------------------------------------------------------------
-- Signals
-------------------------------------------------------------------------------

  signal DReady_I  : std_logic;
  signal DReady_II : std_logic;

  signal valid_addr             : std_logic;
  signal DCache_Enabled_i       : std_logic;
  signal DCache_Enabled_1       : std_logic;
  signal Update_Cache           : std_logic;
  signal Valid_Req              : std_logic;
  signal Valid_Req_1st_Cycle    : std_logic;
  signal cache_updated_allowed  : std_logic;
  signal xx_req_with_update     : std_logic;
  signal xx_access              : std_logic;
  signal xx_valid_data          : std_logic;
  signal xx_access_done         : std_logic;
  signal xx_data                : std_logic_vector(0 to 31);
  signal valid_req_XX           : std_logic;
  signal Valid_Req_1st_Cycle_XX : std_logic;