jump_logic_gti.vhd

Xilinx软核microblaze源码(VHDL)版本7.10

    --
    -- Reg_Test_Equal Reg_Test_Equal_N  Reg_Zero
    --       1              0            is 1 if Reg = 0
    --       0              1            is 1 if Reg /= 0
    --
    -- The rest of the logic is for choosing between different bracn conditions
    --
    --                                                 |  
    --                        _____                 JumpCarry2  
    --    Force2  -----------|     |                  _|_
    --                       |LUT2 |---Force_Jump2---/0 1\ MUXCY 
    --    EX_Valid------*----|     |                 -----    
    --                  |     -----                   | |
    --                  |     _____                   | | 
    --                  -----|     |                  | |
    --                       |LUT2 |---Force_DI2------  |
    --    Force_Val2-------- |     |                    |
    --                        -----                     |
    --                                                  |
    --                                                  |
    --                        _____                     |
    --   Force1   -----------|     |                 JumpCarry
    --                       |     |                   _|_
    --   Use_Reg_Neg_S-------|LUT3 |---Force_Jump1----/0 1\  MUXCY
    --                       |     |                  -----
    --   Reg_Neg---*---------|     |                   | | 
    --             |          -----                    | |
    --             |                                   | |
    --             |          _____                    | | 
    --             ----------|     |                   | |
    --                       |     |---Force_DI1-------  |
    --    Use_Reg_Neg_DI---- |LUT3 |                     |
    --                       |     |                     |
    --    Force_Val1-------- |     |                     |
    --                        -----                      |
    --                                                   |
    --                                                   |
    --                                                Reg_Zero
    --
    -- (Reg_Neg is signal Reg_neg and Reg_Zero is the signal Reg_neg
    --  Reg_Zero_N is fixed with the Reg_Test_Equal and Reg_Test_Equal_N signals
    -----------------------------------------------------------------------------
    --  Cond   Force_Jump2 Force_DI2 Force_Jump1 Force_DI1 Function
    -----------------------------------------------------------------------------
    --  Never      0          0         -         -        Jump := 0
    --  Always     0          1         -         -        Jump := 1
    --  BEQ        1          -         1         -        Jump := Reg_Zero
    --  BNE        1          -         1         -        Jump := Reg_Zero_N
    --  BLT        1          -         0      Reg_Neg     Jump := Reg_Neg
    --  BGE        1          -         0   not(Reg_Neg)   Jump := not(Reg_Neg)
    --  BLE        1          -   not(Reg_Neg)    1        Jump := Reg_Neg or Reg_Zero
    --  BGT        1          -   not(Reg_Neg)    0        Jump := not(Reg_Neg) and Reg_Zero_N
    -- No Instr    0          0         -         -        Jump := 0
    -----------------------------------------------------------------------------
    -----------------------------------------------------------------------------
    --
    --                      |-\           |-\
    --            Reg_Neg---|1 \    |-----|1 \
    --                      |  |----*     |  |-------- Force_Jump1
    --            Vcc-------|0 /    |----O|0 /
    --                      |-/           |-/
    --                       |             |
    --   Use_Reg_Neg_S-------              |
    --                                     |
    --   Force1----------------------------
    -- 
    -- Force_Jump1 = Force1 * not(Use_reg_neg_s) +
    --               Force1 * Use_reg_neg_s * Reg_neg +
    --               not(Force1) * Use_Reg_Neg_s * not(Reg_Neg)
    --               
    --
    -----------------------------------------------------------------------------
    --  Cond   Force2 Force_Val2 Force1 Use_Reg_Neg_S  Function
    -----------------------------------------------------------------------------
    --  Never    0        0         -         -            - 
    --  Always   0        1         -         -            -
    --  BEQ      1        -         1         0       Force_Jump1 = 1
    --  BNE      1        -         1         0       Force_Jump1 = 1
    --  BLT      1        -         0         0       Force_Jump1 = 0
    --  BGE      1        -         0         0       Force_Jump1 = 0
    --  BLE      1        -         0         1       Force_Jump1 = not(Reg_Neg)
    --  BGT      1        -         0         1       Force_Jump1 = not(Reg_Neg)
    -----------------------------------------------------------------------------
    -----------------------------------------------------------------------------
    --
    --                      |-\           |-\
    --            Reg_Neg---|1 \    |-----|1 \
    --                      |  |----*     |  |-------- Force_DI1
    --            Vcc-------|0 /    |----O|0 /
    --                      |-/           |-/
    --                       |             |
    --   Use_Reg_Neg_DI------              |
    --                                     |
    --   Force_Val1------------------------
    -- 
    -- Force_DI1 = Force_Val1 * not(Use_reg_neg_DI) +
    --               Force_Val1 * Use_reg_neg_DI * Reg_neg +
    --               not(Force1_Val1) * Use_Reg_Neg_DI * not(Reg_Neg)
    --               
    -----------------------------------------------------------------------------
    --  Cond   Force2 Force_Val2 Force_Val1 Use_Reg_Neg_DI  Function
    -----------------------------------------------------------------------------
    --  Never    0        0         -         -            - 
    --  Always   0        1         -         -            -
    --  BEQ      1        -         -         -            -
    --  BNE      1        -         -         -            -
    --  BLT      1        -         1         1       Force_DI1 = Reg_Neg
    --  BGE      1        -         0         1       Force_DI1 = not(Reg_Neg)
    --  BLE      1        -         1         0       Force_DI1 = 1
    --  BGT      1        -         0         0       Force_DI1 = 0
    -----------------------------------------------------------------------------
    -----------------------------------------------------------------------------
    -----------------------------------------------------------------------------
    --  Cond    F2 FVal2  F1  Use_S  FVal1 Use_DI  Eq  Eq_N Function
    -----------------------------------------------------------------------------
    --  Never    0   0    -     -      -      -    -    -  FJ2=0,FD2=0
    --  Always   0   1    -     -      -      -    -    -  FJ2=0,FD2=1
    --  BEQ      1   -    1     0      -      -    1    0  FJ2=1,FJ1=1
    --  BNE      1   -    1     0      -      -    0    1  FJ2=1,FJ1=1,Z=not(Z)
    --  BLT      1   -    0     0      1      1    -    -  FJ2=1,FJ1=0,FDI=N
    --  BGE      1   -    0     0      0      1    -    -  FJ2=1,FJ1=0,FDI=not(N)
    --  BLE      1   -    0     1      1      0    1    0  FJ2=1,FJ1=not(N),FD2=
    --  BGT      1   -    0     1      0      0    0    1
    --
    --

    Jump_Decode : process (clk) is
      variable temp_OF : std_logic_vector(BXX_POS_TYPE);
    begin
      if (Clk'event and Clk = '1') then
        if (Reset = '1') then
          ex_op1_cmp_eq      <= true;
          ex_op1_cmp_eq_n    <= false;
          force1             <= '0';
          force_Val1         <= '0';
          use_Reg_Neg_S      <= '0';
          use_Reg_Neg_DI     <= '0';
          force_Val2_N       <= '1';
          force2             <= '0';
        elsif (OF_PipeRun) then
          temp_OF            := OF_Instr(BXX_POS_TYPE);  -- NCVHDL required for case statement
          -- Default values is Never jump condition
          force_Val2_N       <= '1';
          force2             <= '0';
          ex_op1_cmp_eq      <= true;
          ex_op1_cmp_eq_n    <= false;
          force1             <= '0';
          force_Val1         <= '0';
          use_Reg_Neg_S      <= '0';
          use_Reg_Neg_DI     <= '0';

          if (OF_Instr(OPCODE_POS_TYPE) = BXX_DEC) or (OF_Instr(OPCODE_POS_TYPE) = BXXI_DEC) then
            force2 <= '1';
            case temp_OF is

              when BEQ_DEC =>
                force1        <= '1';
                use_Reg_Neg_S <= '0';   -- Force_Jump1 = '1'

              when BNE_DEC =>
                force1             <= '1';
                use_Reg_Neg_S      <= '0';   -- Force_Jump1 = '1'
                ex_op1_cmp_eq      <= false;
                ex_op1_cmp_eq_n    <= true;  -- Reg_Zero is Reg_Zero_N
                
              when BLT_DEC =>
                force1         <= '0';
                use_Reg_Neg_S  <= '0';  -- Force_Jump1 = '0'
                force_Val1     <= '1';
                use_Reg_Neg_DI <= '1';  -- Force_DI1 = Reg_Neg

              when BGE_DEC =>
                force1         <= '0';
                use_Reg_Neg_S  <= '0';  -- Force_Jump1 = '0'
                force_Val1     <= '0';
                use_Reg_Neg_DI <= '1';  -- Force_DI1 = not(Reg_Neg)

              when BLE_DEC =>
                force1         <= '0';
                use_Reg_Neg_S  <= '1';  -- Force_Jump1 = not(Reg_Neg)
                force_Val1     <= '1';
                use_Reg_Neg_DI <= '0';  -- Force_DI1 = '1'

              when BGT_DEC =>
                force1             <= '0';
                use_Reg_Neg_S      <= '1';   -- Force_Jump1 = not(Reg_Neg)
                force_Val1         <= '0';
                use_Reg_Neg_DI     <= '0';   -- Force_DI1 = '0'
                ex_op1_cmp_eq      <= false;
                ex_op1_cmp_eq_n    <= true;  -- Reg_Zero is Reg_Zero_N
              when others => null;
            end case;
          elsif (OF_Instr(OPCODE_POS_TYPE) = BRXX_DEC) or (OF_Instr(OPCODE_POS_TYPE) = BRXXI_DEC) or
            (OF_Instr(OPCODE_POS_TYPE) = RTX_DEC) then
            force_Val2_N <= '0';             -- always
          end if;
        end if;
      end if;
    end process Jump_Decode;

    reg_zero <= '1' when EX_Op1_Zero else '0';
    reg_neg  <= '1' when EX_Op1_Neg  else '0';

    ---------------------------------------------------------------------------
    -- 1st stage of carry logic after the zero detect
    ---------------------------------------------------------------------------
    force_jump1 <= (force1 and not use_Reg_Neg_S) or
                   (force1 and use_Reg_Neg_S and Reg_Neg) or
                   (not(force1) and use_Reg_Neg_S and not (Reg_Neg));

    force_di1 <= (force_val1 and not use_Reg_Neg_DI) or
                 (force_val1 and use_Reg_Neg_DI and Reg_Neg) or
                 (not(force_val1) and use_Reg_Neg_DI and not (Reg_Neg));


    -- jump_carry1 <= Reg_Zero when force_jump1 = '1' else force_di1;
    MUXCY_JUMP_CARRY : MUXCY_L
      port map (
        DI => force_di1,                -- [in]
        CI => Reg_Zero,                 -- [in]
        S  => force_jump1,              -- [in]
        LO => jump_Carry1);             -- [out]


    ---------------------------------------------------------------------------
    -- 2nd stage of carry logic
    ---------------------------------------------------------------------------
    Carry_Stage2: process (EX_Take_Intr_or_Exc, EX_Valid, force2,
                           force_Val2_N) is
    begin  -- process Carry_Stage2
      if (EX_Valid) then
        force_jump2 <= force2;
        force_di2 <= (not force_val2_n);
      else
        force_jump2 <= '0';
        force_di2 <= '0';
      end if;

      -- Branch on interrupts force a branch
      if (EX_Take_Intr_or_Exc) then
        force_jump2 <= '0';             -- Force in a value in the carry chain
        force_di2 <= '1';               -- Force in a '1'
      end if;
    end process Carry_Stage2;
    

    -- jump_carry2 <= jump_carry1 when force_jump2 = '1' else force_di2;
    MUXCY_JUMP_CARRY2 : MUXCY_L
      port map (
        DI => force_di2,                -- [in]
        CI => jump_Carry1,              -- [in]
        S  => force_jump2,              -- [in]
        LO => jump_Carry2);             -- [out]

    ---------------------------------------------------------------------------
    -- 3rd stage of the carry chain
    ---------------------------------------------------------------------------

    -- Don't branch if we are going to take an exception on this instruction
    force_jump3 <= '1' when (not EX_exception) else '0';
    force_di3   <= '0';

    MUXCY_JUMP_CARRY3 : MUXCY_L
      port map (
        DI => force_di3,                -- [in]
        CI => jump_Carry2,              -- [in]
        S  => force_jump3,              -- [in]
        LO => ex_jump_wanted_stdl);     -- [out]

    ---------------------------------------------------------------------------
    -- 4th stage of the carry chain
    ---------------------------------------------------------------------------
    force_jump4 <= '1' when (not IF_Addr_Lookup_MMU) and
                            (not ex_missed_fetch_done_stop_jump) and
                            (of_valid or not EX_Branch_With_Delayslot) and
                            (not ex_jump_q) else '0';
    force_di4   <= '0';

    MUXCY_JUMP_CARRY4 : MUXCY_L
      port map (
        DI => force_di4,                -- [in]
        CI => ex_jump_wanted_stdl,      -- [in]
        S  => force_jump4,              -- [in]
        LO => ex_jump_i_stdl);          -- [out]

    ex_jump_i <= (ex_jump_i_stdl = '1');
    ex_jump_stall_i <= (ex_jump_wanted_stdl = '1') and
                       ((not of_valid and EX_Branch_With_Delayslot) or IF_Addr_Lookup_MMU);

  end generate FPGA_TARGET;

  EX_Op1_CMP_Equal   <= ex_op1_cmp_eq;
  EX_Op1_CMP_Equal_n <= ex_op1_cmp_eq_n;

  EX_Jump            <= ex_jump_i;
  EX_Jump_Stall      <= ex_jump_stall_i;

end architecture IMP;