jump_logic_gti.vhd

Xilinx软核microblaze源码(VHDL)版本7.10

-------------------------------------------------------------------------------
-- $Id: jump_logic_gti.vhd,v 1.1 2007/10/12 09:11:36 stefana Exp $
-------------------------------------------------------------------------------
-- jump_logic_gti.vhd - Entity and architecture
--
--  ***************************************************************************
--  **  Copyright(C) 2003 by Xilinx, Inc. All rights reserved.               **
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--  **  Unmodified source code is guaranteed to place and route,             **
--  **  function and run at speed according to the datasheet                 **
--  **  specification. Source code is provided "as-is", with no              **
--  **  obligation on the part of Xilinx to provide support.                 **
--  **                                                                       **
--  **  Xilinx Hotline support of source code IP shall only include          **
--  **  standard level Xilinx Hotline support, and will only address         **
--  **  issues and questions related to the standard released Netlist        **
--  **  version of the core (and thus indirectly, the original core source). **
--  **                                                                       **
--  **  The Xilinx Support Hotline does not have access to source            **
--  **  code and therefore cannot answer specific questions related          **
--  **  to source HDL. The Xilinx Support Hotline will only be able          **
--  **  to confirm the problem in the Netlist version of the core.           **
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--  **  This copyright and support notice must be retained as part           **
--  **  of this text at all times.                                           **
--  ***************************************************************************
--
-------------------------------------------------------------------------------
-- Filename:        jump_logic_gti.vhd
--
-- Description:     
--                  
-- VHDL-Standard:   VHDL'93
-------------------------------------------------------------------------------
-- Structure:   
--              jump_logic_gti.vhd
--
-------------------------------------------------------------------------------
-- Author:          goran
-- Revision:        $Revision: 1.1 $
-- Date:            $Date: 2007/10/12 09:11:36 $
--
-- History:
--   goran  2005-10-26    First Version
--
-------------------------------------------------------------------------------
-- Naming Conventions:
--      active low signals:                     "*_n"
--      clock signals:                          "clk", "clk_div#", "clk_#x" 
--      reset signals:                          "rst", "rst_n" 
--      generics:                               "C_*" 
--      user defined types:                     "*_TYPE" 
--      state machine next state:               "*_ns" 
--      state machine current state:            "*_cs" 
--      combinatorial signals:                  "*_com" 
--      pipelined or register delay signals:    "*_d#" 
--      counter signals:                        "*cnt*"
--      clock enable signals:                   "*_ce" 
--      internal version of output port         "*_i"
--      device pins:                            "*_pin" 
--      ports:                                  - Names begin with Uppercase 
--      processes:                              "*_PROCESS" 
--      component instantiations:               "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;

--------------------------------------------------------------------------
-- Include MicroBlaze package for data types and ISA constants
--------------------------------------------------------------------------
library Microblaze_v7_10_a;
use Microblaze_v7_10_a.MicroBlaze_ISA.all;
use Microblaze_v7_10_a.MicroBlaze_Types.all;

library unisim;
use unisim.vcomponents.all;

entity jump_logic is
  
  generic (
    C_TARGET : TARGET_FAMILY_TYPE);

  port (
    Clk   : in std_logic;
    Reset : in std_logic;

    OF_PipeRun : in boolean;
    EX_PipeRun : in boolean;

    OF_Valid : in boolean;
    OF_instr : in DATA_TYPE;

    EX_which_branch                 : in std_logic_vector(BXX_POS_TYPE);
    EX_Opcode                       : in OPCODE_TYPE;
    EX_Missed_Fetch_on_Branch_Ended : in boolean;
    EX_Branch_With_Delayslot        : in boolean;
    EX_Take_Intr_or_Exc             : in boolean;
    EX_Valid                        : in boolean;
    EX_Exception                    : in boolean;
    EX_Op1_Neg                      : in boolean;
    EX_Op1_Zero                     : in boolean;
    IF_Addr_Lookup_MMU              : in boolean;

    EX_Op1_CMP_Equal   : out boolean;
    EX_Op1_CMP_Equal_n : out boolean;

    EX_Jump_Stall : out boolean;
    EX_Jump       : out boolean

    );

end entity jump_logic;

architecture IMP of jump_logic is

  signal ex_jump_i                     : rboolean;
  signal ex_jump_stall_i               : rboolean;
  signal ex_jump_q                     : boolean;

  signal ex_op1_cmp_eq                 : rboolean;
  signal ex_op1_cmp_eq_n               : rboolean;

  signal ex_missed_fetch_on_branch_ended_hold : boolean;
  signal ex_missed_fetch_done_stop_jump : boolean;

begin  -- architecture IMP

  -----------------------------------------------------------------------------
  -- Need to hold this signal until the branch instruction has moved away from
  -- EX stage
  -----------------------------------------------------------------------------
  EX_Missed_Fetch_on_Branch_Ended_Hold_DFF: process (Clk) is
  begin -- process EX_Missed_Fetch_on_Branch_Ended_Hold_DFF
    if Clk'event and Clk = '1' then     -- rising clock edge
      if EX_PipeRun then               -- synchronous reset (active high)
        ex_missed_fetch_on_branch_ended_hold <= false;
      elsif (EX_Missed_Fetch_on_Branch_Ended) then
        ex_missed_fetch_on_branch_ended_hold <= true;        
      end if;
    end if;
  end process EX_Missed_Fetch_on_Branch_Ended_Hold_DFF;

  -- This signal stops the ex_jump signal from being active after the actual
  -- branch target address fetch has started
  ex_missed_fetch_done_stop_jump <= ex_missed_fetch_on_branch_ended_hold;

  -----------------------------------------------------------------------------
  -- Need to make sure EX_Jump is not asserted too long to miss instruction
  -- fetches if pipe is stalled in MEM stage
  -----------------------------------------------------------------------------
  EX_Jump_Delay_DFF: process (Clk) is
  begin -- process EX_Jump_Delay_DFF
    if Clk'event and Clk = '1' then  -- rising clock edge
      if EX_PipeRun then             -- synchronous reset (active high)
        ex_jump_q <= false;
      elsif ex_jump_i then
        ex_jump_q <= true;
      end if;
    end if;
  end process EX_Jump_Delay_DFF;


  RTL_TARGET : if (C_TARGET = RTL) generate
    signal ex_jump_wanted : boolean;
  begin
    -----------------------------------------------------------------------------
    -- Branch_CMP_Equal_DFF
    -- What kind of comparison to perform
    ----------------------------------------------------------------------------
    ex_op1_cmp_eq   <= true;
    ex_op1_cmp_eq_n <= false;

    ---------------------------------------------------------------------------
    -- Jump determination process 
    ---------------------------------------------------------------------------
    -----------------------------------------------------------------------------
    --  Cond   Force_Jump2 Force_DI2 Force_Jump1 Force_DI1 Function
    -----------------------------------------------------------------------------
    --  Never      0          0         -         -        Jump := 0
    --  Always     0          1         -         -        Jump := 1
    --  BEQ        1          -         1         -        Jump := Op1_Zero
    --  BNE        1          -         1         -        Jump := not(Op1_Zero)
    --  BLT        1          -         0      Op1_Neg     Jump := Op1_Neg
    --  BGE        1          -         0   not(Op1_Neg)   Jump := not(Op1_Neg)
    --  BLE        1          -   not(Op1_Neg)    1        Jump := Op1_Neg or Op1_Zero
    --  BGT        1          -   not(Op1_Neg)    0        Jump := not(Op1_Neg) and not(Op1_Zero)
    -- No Instr    0          0         -         -        Jump := 0
    -----------------------------------------------------------------------------
    -----------------------------------------------------------------------------
    EX_Jump_PROCESS : process (EX_Op1_Neg, EX_Op1_Zero, EX_Take_Intr_or_Exc,
                               EX_exception, EX_opcode, EX_valid,
                               EX_which_branch) is
    begin
      ex_jump_wanted <= false;

      if (EX_opcode = BXX_DEC) or (EX_opcode = BXXI_DEC) then
        -- branch                            or      branch imm
        case EX_which_branch is
          when BEQ_DEC =>               -- branch equal
            ex_jump_wanted <= EX_Op1_Zero;
          when BNE_DEC =>               -- branch not-equal
            ex_jump_wanted <= not EX_Op1_Zero;
            -- If ex_op1_cmp_eq_n
            -- ex_jump <= EX_Op1_Zero;
          when BLT_DEC =>               -- branch less than
            ex_jump_wanted <= EX_Op1_Neg;
          when BGE_DEC =>               -- branch greater than or equal
            ex_jump_wanted <= not EX_Op1_Neg;
          when BLE_DEC =>               -- branch less than or equal
            ex_jump_wanted <= EX_Op1_Neg or EX_Op1_Zero;
          when BGT_DEC =>               -- branch greater than
            ex_jump_wanted <= not (EX_Op1_Neg or EX_Op1_Zero);
            -- If ex_op1_cmp_eq_n
            -- ex_jump <= not(EX_Op1_Neg) and EX_Op1_Zero;
          when others => null;
        end case;
      elsif (EX_opcode = BRXX_DEC) or (EX_opcode = BRXXI_DEC) or
        (EX_opcode = RTX_DEC) then
        -- Always branch on unconditional branch (brxx, brxxi), breaks (brk, brki),
        -- and returns rtxd
        ex_jump_wanted <= true;
      end if;

      -- Don't branch at all if the instruction in the ex stage isn't valid
      if not EX_Valid then
        ex_jump_wanted <= false;
      end if;

      -- Branch on interrupts
      if (EX_Take_Intr_or_Exc) then
        ex_jump_wanted <= true;
      end if;

      -- Don't branch if we are going to take an exception on this instruction
      if (EX_exception) then
        ex_jump_wanted <= false;
      end if;

    end process EX_Jump_PROCESS;

    -----------------------------------------------------------------------------
    -- If the branch has a delay slot, don't jump until the delay slot
    -- instruction is in the of_stage
    -----------------------------------------------------------------------------
    ex_jump_i <= (not IF_Addr_Lookup_MMU) and
                 (not ex_missed_fetch_done_stop_jump) and (
                 (EX_Branch_With_Delayslot and ex_jump_wanted and of_valid) or
                 (not EX_Branch_With_Delayslot and ex_jump_wanted)) and
                 (not ex_jump_q);

    ex_jump_stall_i <= ex_jump_wanted and not ex_jump_i;
    
  end generate RTL_TARGET;

  -----------------------------------------------------------------------------
  -- FPGA implementation is very different from RTL version
  -- The FPGA implementation is using the carry-chain for all coding since the
  -- EX_Op1_Zero is coming from a carry-chain.
  -- This also changes the decoding in the OF stage
  -----------------------------------------------------------------------------
  FPGA_TARGET : if (C_TARGET /= RTL) generate

    signal reg_zero : std_logic;
    signal reg_neg  : std_logic;

    signal force1         : std_logic;
    signal force_Val1     : std_logic;
    signal force2         : std_logic;
    signal force_Val2_N   : std_logic;
    signal use_Reg_Neg_S  : std_logic;
    signal use_Reg_Neg_DI : std_logic;
    signal force_jump1    : std_logic;
    signal force_DI1      : std_logic;
    signal force_jump2    : std_logic;
    signal force_DI2      : std_logic;
    signal force_jump3    : std_logic;
    signal force_DI3      : std_logic;
    signal force_jump4    : std_logic;
    signal force_DI4      : std_logic;

    signal jump_carry1         : std_logic;
    signal jump_carry2         : std_logic;
    signal ex_jump_wanted_stdl : std_logic;
    signal ex_jump_i_stdl      : std_logic;
    
  begin
    -----------------------------------------------------------------------------
    -- Hard code jump decision logic using carry chain and xorcy gate
    -----------------------------------------------------------------------------
    --
    -- By driving the Reg_Test_Equal and the Reg_Test_Equal_N signals to 0/1 or
    -- 1/0, I can determine if the zero_detect logic should detect equal to zero
    -- or not equal to zero.