alu_bit.vhd

Xilinx软核microblaze源码(VHDL)版本7.10

--SINGLE_FILE_TAG
-------------------------------------------------------------------------------
-- $Id: alu_bit.vhd,v 1.1 2007/10/12 09:11:36 stefana Exp $
-------------------------------------------------------------------------------
-- alu.vhd - entity/architecture pair
-------------------------------------------------------------------------------
--
-- ****************************************************************************
-- ** Copyright(C) 2001-2005 by Xilinx, Inc. All rights reserved.
-- **
-- ** This text contains proprietary, confidential information of
-- ** Xilinx, Inc. , is distributed by under license from Xilinx, Inc.,
-- ** and may be used, copied and/or disclosed only pursuant to the
-- ** terms of a valid license agreement with Xilinx, Inc. 
-- **
-- ** Unmodified source code is guaranteed to place and route, 
-- ** function and run at speed according to the datasheet
-- ** specification. Source code is provided "as-is", with no
-- ** obligation on the part of Xilinx to provide support.
-- **
-- ** Xilinx Hotline support of source code IP shall only include
-- ** standard level Xilinx Hotline support, and will only address
-- ** issues and questions related to the standard released Netlist
-- ** version of the core (and thus indirectly, the original core source
-- **
-- ** The Xilinx Support Hotline does not have access to source
-- ** code and therefore cannot answer specific questions related
-- ** to source HDL. The Xilinx Support Hotline will only be able
-- ** to confirm the problem in the Netlist version of the core.
-- **
-- ** This copyright and support notice must be retained as part
-- ** of this text at all times.
-- ****************************************************************************
--
-------------------------------------------------------------------------------
-- Filename:        alu_bit.vhd
-- Version:         v1.00a
-- Description:     Implements 1 bit of the ALU
--                  
-------------------------------------------------------------------------------
-- Structure:   
--
-------------------------------------------------------------------------------
-- Author:          goran
-- History:
--   goran  01-22-2001    First version of entity
--   goran  03-06-2001    First Version of arch
--   BLT    04-16-2001    Changed M_ABus FFs to have synch reset
--   LTG    04-15-2005    Modified for MicroBlaze GTi
--   rikard 08-28-2006    Merge between GTi and area tracks
--
-------------------------------------------------------------------------------
-- Naming Conventions:
--      active low signals:                     "*_n"
--      clock signals:                          "clk", "*_clk"
--      reset signals:                          "rst", "*_rst", "reset"
--      generics:                               All uppercase, starting with: "C_"
--      constants:                              All uppercase, not starting with: "C_"
--      state machine next state:               "*_next_state"
--      state machine current state:            "*_curr_state"
--      pipelined signals:                      "*_d#"
--      counter signals:                        "*_cnt_*" , "*_counter_*", "*_count_*"
--      internal version of output port:        "*_i"
--      ports:                                  Names begin with uppercase
--      component instantiations:               "<ENTITY_>I_<#|FUNC>" , "ENTITY>_I#" 
--
-- Signals starting with IF, OF, EX, MEM, or WB indicate that they start in that
-- stage:
--
--    IF                      -- instruction fetch
--    OF                      -- operand fetch
--    EX                      -- execute
--    MEM                     -- memory
--    WB                      -- write back
-------------------------------------------------------------------------------

library IEEE;
use IEEE.std_logic_1164.all;
library Microblaze_v7_10_a;
use Microblaze_v7_10_a.MicroBlaze_Types.all;


library unisim;
use unisim.vcomponents.all;

-------------------------------------------------------------------------------
-- Port declarations
-------------------------------------------------------------------------------

entity ALU_Bit is

  generic (
    C_TARGET   : TARGET_FAMILY_TYPE;
    C_LAST_BIT : boolean := false
    );
  port (
    EX_Op1         : in  std_logic;
    EX_Op2         : in  std_logic;
    EX_ALU_Op      : in  std_logic_vector(0 to 1);
    EX_CarryIn     : in  std_logic;
    EX_CMP_Op      : in  boolean;
    EX_Unsigned_Op : in  boolean;
    EX_Result      : out std_logic;
    EX_CarryOut    : out std_logic
  );

end entity ALU_Bit;

-------------------------------------------------------------------------------
-- Architecture section
-------------------------------------------------------------------------------

architecture IMP of ALU_Bit is


  signal alu_AddSub : std_logic;
  signal op2_is_1   : std_logic;

  signal ex_result_i : std_logic;


-------------------------------------------------------------------------------
-- Begin architecture
-------------------------------------------------------------------------------

begin  -- IMP

  -----------------------------------------------------------------------------
  -- Generating the Arithmetic operations
  -----------------------------------------------------------------------------

  -- EX_ALU_Op
  -- 00 => EX_Op1
  -- 01 => EX_Op2
  -- 10 => EX_Op2 + EX_Op1
  -- 11 => EX_Op2 - EX_Op1
  --
  --                  Karnough map
  --
  --                           bit 1,0
  --  bit 3,2             ALU_Op(MSB), Op2(I)
  --  ALU_Op(LSB),Op1(I)  00  01  11  10 
  --            00         0   0   1   0  1000
  --            01         1   1   0   1  0111
  --            11         0   1   1   0  1010
  --            10         0   1   0   1  0110
  -- Init String = 1010 0110 0111 1000 (A678)
  ---------------------------------------------------------------------------
  -----------------------------------------------------------------------------
  -- Handle bits 31 to 1. Bit 0 is different to support CMPU
  -----------------------------------------------------------------------------
  Not_Last_Bit : if not C_LAST_BIT generate
  begin  -- generate Not_Last_Bit

    -- pass Op1, pass Op2, add or sub bitwise based on EX_ALU_Op
    I_ALU_LUT : LUT4
      generic map(
        INIT => X"A678"
        )
      port map (
        O  => alu_AddSub,                   -- [out]
        I0 => EX_Op2,                       -- [in]
        I1 => EX_ALU_Op(EX_ALU_Op'left),    -- [in]
        I2 => EX_Op1,                       -- [in]
        I3 => EX_ALU_Op(EX_ALU_Op'right));  -- [in]

    -- Confirm that Op2 is '1' for carry calculation
    MULT_AND_I : MULT_AND
      port map (
        I0 => EX_Op2,                     -- [in]
        I1 => EX_ALU_Op(EX_ALU_Op'left),  -- [in]
        LO => op2_is_1);                   -- [out]

    -- If AddSub result is 0 then there must be a carry out if Op2 is '1'
    -- If AddSub result is 1 then there must be a carryin for a carry out
    MUXCY_I : MUXCY_L
      port map (
        DI => op2_is_1,
        CI => EX_CarryIn,
        S  => alu_AddSub,
        LO => EX_CarryOut);

    -- Merge addsub result with carry in to get final result
    XOR_I : XORCY
      port map (
        LI => alu_AddSub,
        CI => EX_CarryIn,
        O  => ex_result_i);

    EX_Result <= ex_result_i;

  end generate Not_Last_Bit;


  -----------------------------------------------------------------------------
  -- Handle most significant bit (different for unsigned compare)
  -----------------------------------------------------------------------------
  Last_Bit_VirtexII : if C_LAST_BIT generate

    signal invert_result            : std_logic;
    signal maintain_sign_n          : std_logic;  -- in a compare operation the
                                                  -- sign bit should be
                                                  -- maintained even if there
                                                  -- is a overflow or undeflow
    signal alu_AddSub_1             : std_logic;
    signal compare_operation        : std_logic;
    signal unsigned_sign_correction : std_logic;
    
  begin  -- generate Last_Bit_VirtexII

    unsigned_sign_correction <= '1' when EX_Unsigned_Op else '0';
    compare_operation        <= '1' when EX_CMP_Op else '0';
    maintain_sign_n          <= not (compare_operation and (EX_Op1 xor EX_Op2));

    ---------------------------------------------------------------------------
    -- alu_addsub result should be inverted if there is an input carry (normal
    -- arithmetic case) or if the operation is a CMPU
    ---------------------------------------------------------------------------
    Pre_MUXCY_I : MUXCY_L
      port map (
        DI => unsigned_sign_correction,
        CI => EX_CarryIn,
        S  => maintain_sign_n,
        LO => invert_result);

    -- Perform bit-wise add, sub, pass op1 and pass op2
    I_ALU_LUT_1 : LUT4
      generic map(
        INIT => X"A678"
        )
      port map (
        O  => alu_AddSub_1,                 -- [out]
        I0 => EX_Op2,                       -- [in]
        I1 => EX_ALU_Op(EX_ALU_Op'left),    -- [in]
        I2 => EX_Op1,                       -- [in]
        I3 => EX_ALU_Op(EX_ALU_Op'right));  -- [in]

    ---------------------------------------------------------------------------
    --                  
    -- maintain_sign_n  EX_Result
    --       0           EX_Op2
    --       1           alu_AddSub_1
    --
    -- 
    -- 
    --                               ALU_Op(0) Op2
    -- alu_AddSub_1,maintain_sign_n  00  01  11  10
    --                          00    0   1   1   0 = 1010
    --                          01    0   0   0   0 = 0000
    --                          11    1   1   1   1 = 1111
    --                          10    0   1   1   0 = 1010
    -- 
    -- INIT = 1111 1010 0000 1010 = FA0A
    ---------------------------------------------------------------------------

    -- select if sign bit should be maintained for compare or be arithmetic
    -- result for addsub
    I_ALU_LUT_2 : LUT4
      generic map(
        INIT => X"FA0A"
        )
      port map (
        O  => alu_AddSub,                 -- [out]
        I0 => EX_Op2,                     -- [in]
        I1 => EX_ALU_Op(EX_ALU_Op'left),  -- don't care, just for 4-LUT equation
        I2 => maintain_sign_n,            -- [in]
        I3 => alu_AddSub_1);              -- [in]

    -- Confirm that Op2 is '1' for carry calculation
    MULT_AND_I : MULT_AND
      port map (
        I0 => EX_Op2,                     -- [in]
        I1 => EX_ALU_Op(EX_ALU_Op'left),  -- [in]
        LO => op2_is_1);                   -- [out]

    -- If addsub_1 result is 0 requires one op2=1, or
    -- if addsub_1 result is 1 requires carryin = 1 then a carry out should be
    -- generated
    MUXCY_I : MUXCY_L
      port map (
        DI => op2_is_1,
        CI => invert_result,
        S  => alu_AddSub,
        LO => EX_CarryOut);

    ---------------------------------------------------------------------------
    -- for CMPU invert Op2 if (Op1 xor Op2) = 1
    -- for other cases: invert result based on carry-in
    ---------------------------------------------------------------------------
    XOR_I : XORCY
      port map (
        LI => alu_AddSub,
        CI => invert_result,
        O  => ex_result_i);

    EX_Result <= ex_result_i;

  end generate Last_Bit_VirtexII;

end architecture IMP;