zero_detect_gti.vhd

Xilinx软核microblaze源码(VHDL)版本7.10

--SINGLE_FILE_TAG
-------------------------------------------------------------------------------
-- $Id: zero_detect_gti.vhd,v 1.1 2007/10/12 09:11:36 stefana Exp $
-------------------------------------------------------------------------------
-- zero_detect.vhd - entity/architecture pair
-------------------------------------------------------------------------------
--
-- ****************************************************************************
-- ** Copyright(C) 2001-2005 by Xilinx, Inc. All rights reserved.
-- **
-- ** This text contains proprietary, confidential information of
-- ** Xilinx, Inc. , is distributed by under license from Xilinx, Inc.,
-- ** and may be used, copied and/or disclosed only pursuant to the
-- ** terms of a valid license agreement with Xilinx, Inc. 
-- **
-- ** Unmodified source code is guaranteed to place and route, 
-- ** function and run at speed according to the datasheet
-- ** specification. Source code is provided "as-is", with no
-- ** obligation on the part of Xilinx to provide support.
-- **
-- ** Xilinx Hotline support of source code IP shall only include
-- ** standard level Xilinx Hotline support, and will only address
-- ** issues and questions related to the standard released Netlist
-- ** version of the core (and thus indirectly, the original core source
-- **
-- ** The Xilinx Support Hotline does not have access to source
-- ** code and therefore cannot answer specific questions related
-- ** to source HDL. The Xilinx Support Hotline will only be able
-- ** to confirm the problem in the Netlist version of the core.
-- **
-- ** This copyright and support notice must be retained as part
-- ** of this text at all times.
-- ****************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: zero_detect.vhd
-- Version: v2.00a
-- Description: Detect if a DATA_TYPE signal is zero
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:   
--              zero_detect.vhd
--
-------------------------------------------------------------------------------
-- Author:          goran
-- History:
--   goran  2001-03-05    - First Version
--   BJS    2005-04-07
-- ^^^^^^
--                        Updated for new pipeline
-- ~~~~~~
--
-------------------------------------------------------------------------------
-- Naming Conventions:
--      active low signals:                     "*_n"
--      clock signals:                          "clk", "*_clk"
--      reset signals:                          "rst", "*_rst", "reset"
--      generics:                               All uppercase, starting with: "C_"
--      constants:                              All uppercase, not starting with: "C_"
--      state machine next state:               "*_next_state"
--      state machine current state:            "*_curr_state"
--      pipelined signals:                      "*_d#"
--      counter signals:                        "*_cnt_*" , "*_counter_*", "*_count_*"
--      internal version of output port:        "*_i"
--      ports:                                  Names begin with uppercase
--      component instantiations:               "<ENTITY_>I_<#|FUNC>" , "ENTITY>_I#" 
--
-- Signals starting with IF, OF, EX, MEM, or WB indicate that they start in that
-- stage:
--
--    IF                      -- instruction fetch
--    OF                      -- operand fetch
--    EX                      -- execute
--    MEM                     -- memory
--    WB                      -- write back
-------------------------------------------------------------------------------

library IEEE;
use IEEE.std_logic_1164.all;

--------------------------------------------------------------------------
-- Include MicroBlaze package for data types
--------------------------------------------------------------------------
library Microblaze_v7_10_a;
use Microblaze_v7_10_a.MicroBlaze_Types.all;

library unisim;
use unisim.vcomponents.all;

-------------------------------------------------------------------------------
-- Port Declaration
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Definition of Generics:
--    C_TARGET                -- Device family
--
-- Definition of Ports:
--
--    EX_Op1_CMP_Equal        -- Test for equality
--    EX_Op1_CMP_Equal_n      -- Test for inequality
--    EX_Branch_CMP_Op1       -- Ra+forwarding to test if zero
--    EX_Op1_Zero             -- Is Ra zero?
--
-------------------------------------------------------------------------------
entity Zero_Detect_gti is
  generic (
    C_TARGET : TARGET_FAMILY_TYPE
  );
  port (
    -- Zero flag signals
    EX_Op1_CMP_Equal   : in  boolean;
    EX_Op1_CMP_Equal_n : in  boolean;
    EX_Branch_CMP_Op1  : in  DATA_TYPE;
    EX_Op1_Zero        : out boolean
    );
end entity Zero_Detect_gti;

--------------------------------------------------------------------------
-- Architecture section
--------------------------------------------------------------------------

architecture IMP of Zero_Detect_gti is

  constant C_BITS_PER_LUT : integer:= Family_To_LUT_Size(C_TARGET);
  
  signal ex_op1_zero_i : rboolean;
  
begin

  RTL_Target : if (C_TARGET = RTL) generate
    ----------------------------------------
    -- Zero_Detect_PROCESS
    -- Detect if DATA_TYPE is zero
    ----------------------------------------
    Zero_Detect_PROCESS : process (EX_Branch_CMP_Op1,
                                  EX_Op1_CMP_Equal, EX_Op1_CMP_Equal_n) is
      constant ZERO : DATA_TYPE := (others => '0');
    begin
      if EX_Branch_CMP_Op1 = ZERO then
        -- Zero
        -- True if testing equal
        ex_op1_zero_i <= EX_Op1_CMP_Equal;
      else
        -- Non-zero
        -- True if testing not-equal
        ex_op1_zero_i <= EX_Op1_CMP_Equal_n;
      end if;
    end process Zero_Detect_PROCESS;
  end generate RTL_Target;

  FPGA_Target : if (C_TARGET /= RTL) generate
    constant DATA_SIZE            : natural := EX_Branch_CMP_Op1'length;
    constant NR_OF_NIBBLES        : natural := (DATA_SIZE+C_BITS_PER_LUT-1)/C_BITS_PER_LUT;
    
    signal   EX_Branch_CMP_Op1_I  : std_logic_vector(0 to NR_OF_NIBBLES * C_BITS_PER_LUT -1);
    signal   reg_test_Equal       : std_logic;
    signal   reg_Test_Equal_N     : std_logic;
    signal   nibble_Zero          : std_logic_vector(NR_OF_NIBBLES-1 downto 0);
    signal   zero_CI              : std_logic_vector(NR_OF_NIBBLES downto 0);
    signal   zero_C               : std_logic;      
  begin
    -- Select if we are locking for Op1=0 or Op1/=0.
    reg_test_Equal   <= '1' when EX_Op1_CMP_Equal   else '0';
    reg_Test_Equal_N <= '1' when EX_Op1_CMP_Equal_n else '0';

    Part_Of_Zero_Carry_Start : MUXCY_L
      port map (
        DI => '0',                    -- [in  std_logic]
        CI => '1',                    -- [in  std_logic]
        S  => Reg_test_Equal,         -- [in  std_logic]
        LO => zero_CI(0));            -- [out std_logic]

    zero_C <= Reg_Test_Equal_N;

    -- Expand with zero bits if necessary.
    Expand_Bus: process(Ex_Branch_CMP_Op1) is
    begin  -- process assign_sigs
      Ex_Branch_CMP_Op1_I                   <= (others => '0');
      Ex_Branch_CMP_Op1_I(0 to DATA_SIZE-1) <= Ex_Branch_CMP_Op1;
    end process Expand_Bus;
    
    -- Detect Zero in carry chain.
    Zero_Detecting : for I in 0 to NR_OF_NIBBLES-1 generate
    begin
      -- Combine the signals that fit into one LUT.
      Compare_All_Bits: process(Ex_Branch_CMP_Op1_I)
        variable sel_I   : std_logic;
      begin
        sel_I  :=  '0';
        Compare_Bits: for J in C_BITS_PER_LUT - 1 downto 0 loop
          sel_I  := sel_I or Ex_Branch_CMP_Op1_I(NR_OF_NIBBLES * C_BITS_PER_LUT - I*C_BITS_PER_LUT - C_BITS_PER_LUT + J);
        end loop Compare_Bits;
        nibble_Zero(I) <= not sel_I;
      end process Compare_All_Bits;
      
      I_Part_Of_Zero_Detect : MUXCY_L
        port map (
          DI => zero_C,               -- [in  std_logic]
          CI => zero_CI(I),           -- [in  std_logic]
          S  => nibble_Zero(I),       -- [in  std_logic]
          LO => zero_CI(I+1));        -- [out std_logic]

    end generate Zero_Detecting;
    
    -- The detected result.
    ex_op1_zero_i <= (zero_CI(NR_OF_NIBBLES) = '1');

  end generate FPGA_Target;

  EX_Op1_Zero <= ex_op1_zero_i;

end architecture IMP;