timer.vhd

基于硬件描述性语言vhdl的定时器timer的设计

Library IEEE;
   Use IEEE.std_logic_1164.all;
   Use IEEE.std_logic_unsigned.all;

   Entity timer Is
      Port (  reset    : In     std_logic;
clk     : In     std_logic;
Dbus    : Inout   std_logic_vector(15 downto 0);
Abus    : In      std_logic_vector(13 downto 0);
  rd     : In      std_logic;
  wr     : In     std_logic;
        timer_en     :in      std_logic;
        timer_pt     :out      std_logic    --timer  Interrupt
 );
End timer;

Architecture timer Of timer Is
Signal ts_temp:  std_logic_vector(7 downto 0);
Signal tscale:   std_logic_vector(7 downto 0);
Signal tperiod:  std_logic_vector(15 downto 0);
Signal tcount:   std_logic_vector(15 downto 0);
Signal ts_zero:   std_logic;
Signal tc_zero:   std_logic;
Begin
    timer_pt <= tc_zero;

    bus_readIng:
    Process(rd,Abus)
    Begin
       If rd='0' and Abus="11111111111011" Then       --0x3ffb
          Dbus<="00000000"&ts_temp;
       Elsif rd='0' and Abus="11111111111100" Then    --0x3ffc
          Dbus<=tcount;
       Elsif rd='0'and Abus="11111111111101" Then    --0x3ffd
          Dbus<=tperiod; 
         Else
          Dbus<="ZZZZZZZZZZZZZZZZ";
      End If;
     End Process bus_readIng;

     Ts_temp_P:
     Process(clk,reset)
     Begin
          If reset='0' Then
             Ts_temp<="00000000";
          Elsif clk'event and clk='1' Then
               If Abus="11111111111011" and wr='0' Then
                   Ts_temp<=Dbus(7 downto 0);
               End If;
           End If;
      End Process;

      Tscale_P:
      Process(clk,reset)
      Begin
          If reset='0' Then
              tscale<="00000000";
          Elsif clk'event and clk='1'Then
              If Abus="11111111111011" and wr='0' Then
                 tscale<=Dbus(7 downto 0);
              Elsif timer_en='1' Then
                 If tscale="00000000" Then   --should be set first
                     tscale<=ts_temp;
                 Else
                     tscale<=tscale-'1';
                 End If;
               End If;
           End If;
       End Process tscale_P;

       Tperiod_P:
       Process(clk,reset)
       Begin
           If reset='0' Then
               Tperiod<="0000000000000000";
           Elsif clk'event and clk='1'then        
       If wr='0' and Abus="11111111111101" Then  --0x3ffd
                   tperiod<=Dbus;
               End If;
           End If;
       End Process;

       Tcount_P:
       Process(clk,reset)
       Begin
           If reset='0' Then
              tcount<="0000000000000000";
           Elsif clk'event and clk='1' Then
              If Abus="11111111111100" and wr='0' Then --0x3ffc
                tcount<=Dbus;
              Elsif timer_en='1' Then
                    If tcount="0000000000000000" and tscale="00000000" Then
                                                 --should be set first
                     tcount<=tperiod;
                Elsif ts_zero='1' Then
                     tcount<=tcount-'1';
                End If;
              End If;
            End If;
        End Process;

        ts_zero_P:
        Process(clk,reset)
        Begin
            If reset='0' Then
                ts_zero<='0';
            Elsif clk'event and clk='1' Then
                If tscale="00000001" Then
                    ts_zero<='1';
                Else
                    ts_zero<='0';
                End If;
            End If;
         End Process;

         tc_zero_P:
         Process(clk,reset)
         Begin
             If reset='0' Then
                 tc_zero<='0';
             Elsif clk'event and clk='1' Then
If tcount="0000000000000000" and tscale="00000000" and timer_en='1' Then
                       tc_zero<='1';
                 Else
                       tc_zero<='0';
                 End If;
             End If;
          End Process;

End timer;