usb2_v.map.summary

USB2_V例子工程是一个FPGA数据通过USB2.0传输到PC机的示例.

Analysis & Synthesis Status : Successful - Mon May 18 11:47:34 2009
Quartus II Version : 7.2 Build 207 03/18/2008 SP 3 SJ Full Version
Revision Name : USB2_V
Top-level Entity Name : USB2_V
Family : Cyclone II
Total logic elements : 41
    Total combinational functions : 41
    Dedicated logic registers : 35
Total registers : 35
Total pins : 25
Total virtual pins : 0
Total memory bits : 0
Embedded Multiplier 9-bit elements : 0
Total PLLs : 0