📄 prev_cmp_usb2_v.tan.qmsg
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{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register usb2_test:inst1\|cnt2\[6\] register usb2_test:inst1\|cnt2\[4\] 205.21 MHz 4.873 ns Internal " "Info: Clock \"clk\" has Internal fmax of 205.21 MHz between source register \"usb2_test:inst1\|cnt2\[6\]\" and destination register \"usb2_test:inst1\|cnt2\[4\]\" (period= 4.873 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.609 ns + Longest register register " "Info: + Longest register to register delay is 4.609 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns usb2_test:inst1\|cnt2\[6\] 1 REG LCFF_X59_Y22_N13 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X59_Y22_N13; Fanout = 3; REG Node = 'usb2_test:inst1\|cnt2\[6\]'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { usb2_test:inst1|cnt2[6] } "NODE_NAME" } } { "usb2_test.v" "" { Text "E:/wt/workspace/mywork/USB2_V/usb2_test.v" 34 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.092 ns) + CELL(0.577 ns) 1.669 ns usb2_test:inst1\|Equal0~146 2 COMB LCCOMB_X60_Y22_N4 1 " "Info: 2: + IC(1.092 ns) + CELL(0.577 ns) = 1.669 ns; Loc. = LCCOMB_X60_Y22_N4; Fanout = 1; COMB Node = 'usb2_test:inst1\|Equal0~146'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.669 ns" { usb2_test:inst1|cnt2[6] usb2_test:inst1|Equal0~146 } "NODE_NAME" } } { "usb2_test.v" "" { Text "E:/wt/workspace/mywork/USB2_V/usb2_test.v" 28 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.368 ns) + CELL(0.589 ns) 2.626 ns usb2_test:inst1\|Equal0~149 3 COMB LCCOMB_X60_Y22_N28 2 " "Info: 3: + IC(0.368 ns) + CELL(0.589 ns) = 2.626 ns; Loc. = LCCOMB_X60_Y22_N28; Fanout = 2; COMB Node = 'usb2_test:inst1\|Equal0~149'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.957 ns" { usb2_test:inst1|Equal0~146 usb2_test:inst1|Equal0~149 } "NODE_NAME" } } { "usb2_test.v" "" { Text "E:/wt/workspace/mywork/USB2_V/usb2_test.v" 28 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.380 ns) + CELL(0.206 ns) 3.212 ns usb2_test:inst1\|Equal0~150 4 COMB LCCOMB_X60_Y22_N14 16 " "Info: 4: + IC(0.380 ns) + CELL(0.206 ns) = 3.212 ns; Loc. = LCCOMB_X60_Y22_N14; Fanout = 16; COMB Node = 'usb2_test:inst1\|Equal0~150'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.586 ns" { usb2_test:inst1|Equal0~149 usb2_test:inst1|Equal0~150 } "NODE_NAME" } } { "usb2_test.v" "" { Text "E:/wt/workspace/mywork/USB2_V/usb2_test.v" 28 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.542 ns) + CELL(0.855 ns) 4.609 ns usb2_test:inst1\|cnt2\[4\] 5 REG LCFF_X59_Y22_N9 3 " "Info: 5: + IC(0.542 ns) + CELL(0.855 ns) = 4.609 ns; Loc. = LCFF_X59_Y22_N9; Fanout = 3; REG Node = 'usb2_test:inst1\|cnt2\[4\]'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.397 ns" { usb2_test:inst1|Equal0~150 usb2_test:inst1|cnt2[4] } "NODE_NAME" } } { "usb2_test.v" "" { Text "E:/wt/workspace/mywork/USB2_V/usb2_test.v" 34 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.227 ns ( 48.32 % ) " "Info: Total cell delay = 2.227 ns ( 48.32 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.382 ns ( 51.68 % ) " "Info: Total interconnect delay = 2.382 ns ( 51.68 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.609 ns" { usb2_test:inst1|cnt2[6] usb2_test:inst1|Equal0~146 usb2_test:inst1|Equal0~149 usb2_test:inst1|Equal0~150 usb2_test:inst1|cnt2[4] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "4.609 ns" { usb2_test:inst1|cnt2[6] {} usb2_test:inst1|Equal0~146 {} usb2_test:inst1|Equal0~149 {} usb2_test:inst1|Equal0~150 {} usb2_test:inst1|cnt2[4] {} } { 0.000ns 1.092ns 0.368ns 0.380ns 0.542ns } { 0.000ns 0.577ns 0.589ns 0.206ns 0.855ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 3.190 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 3.190 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.090 ns) 1.090 ns clk 1 CLK PIN_L1 1 " "Info: 1: + IC(0.000 ns) + CELL(1.090 ns) = 1.090 ns; Loc. = PIN_L1; Fanout = 1; CLK Node = 'clk'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "USB2_V.bdf" "" { Schematic "E:/wt/workspace/mywork/USB2_V/USB2_V.bdf" { { 264 -112 56 280 "clk" "" } { 136 264 328 152 "clk" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.239 ns) + CELL(0.000 ns) 1.329 ns clk~clkctrl 2 COMB CLKCTRL_G2 35 " "Info: 2: + IC(0.239 ns) + CELL(0.000 ns) = 1.329 ns; Loc. = CLKCTRL_G2; Fanout = 35; COMB Node = 'clk~clkctrl'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.239 ns" { clk clk~clkctrl } "NODE_NAME" } } { "USB2_V.bdf" "" { Schematic "E:/wt/workspace/mywork/USB2_V/USB2_V.bdf" { { 264 -112 56 280 "clk" "" } { 136 264 328 152 "clk" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.195 ns) + CELL(0.666 ns) 3.190 ns usb2_test:inst1\|cnt2\[4\] 3 REG LCFF_X59_Y22_N9 3 " "Info: 3: + IC(1.195 ns) + CELL(0.666 ns) = 3.190 ns; Loc. = LCFF_X59_Y22_N9; Fanout = 3; REG Node = 'usb2_test:inst1\|cnt2\[4\]'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.861 ns" { clk~clkctrl usb2_test:inst1|cnt2[4] } "NODE_NAME" } } { "usb2_test.v" "" { Text "E:/wt/workspace/mywork/USB2_V/usb2_test.v" 34 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.756 ns ( 55.05 % ) " "Info: Total cell delay = 1.756 ns ( 55.05 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.434 ns ( 44.95 % ) " "Info: Total interconnect delay = 1.434 ns ( 44.95 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.190 ns" { clk clk~clkctrl usb2_test:inst1|cnt2[4] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.190 ns" { clk {} clk~combout {} clk~clkctrl {} usb2_test:inst1|cnt2[4] {} } { 0.000ns 0.000ns 0.239ns 1.195ns } { 0.000ns 1.090ns 0.000ns 0.666ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 3.190 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 3.190 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.090 ns) 1.090 ns clk 1 CLK PIN_L1 1 " "Info: 1: + IC(0.000 ns) + CELL(1.090 ns) = 1.090 ns; Loc. = PIN_L1; Fanout = 1; CLK Node = 'clk'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "USB2_V.bdf" "" { Schematic "E:/wt/workspace/mywork/USB2_V/USB2_V.bdf" { { 264 -112 56 280 "clk" "" } { 136 264 328 152 "clk" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.239 ns) + CELL(0.000 ns) 1.329 ns clk~clkctrl 2 COMB CLKCTRL_G2 35 " "Info: 2: + IC(0.239 ns) + CELL(0.000 ns) = 1.329 ns; Loc. = CLKCTRL_G2; Fanout = 35; COMB Node = 'clk~clkctrl'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.239 ns" { clk clk~clkctrl } "NODE_NAME" } } { "USB2_V.bdf" "" { Schematic "E:/wt/workspace/mywork/USB2_V/USB2_V.bdf" { { 264 -112 56 280 "clk" "" } { 136 264 328 152 "clk" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.195 ns) + CELL(0.666 ns) 3.190 ns usb2_test:inst1\|cnt2\[6\] 3 REG LCFF_X59_Y22_N13 3 " "Info: 3: + IC(1.195 ns) + CELL(0.666 ns) = 3.190 ns; Loc. = LCFF_X59_Y22_N13; Fanout = 3; REG Node = 'usb2_test:inst1\|cnt2\[6\]'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.861 ns" { clk~clkctrl usb2_test:inst1|cnt2[6] } "NODE_NAME" } } { "usb2_test.v" "" { Text "E:/wt/workspace/mywork/USB2_V/usb2_test.v" 34 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.756 ns ( 55.05 % ) " "Info: Total cell delay = 1.756 ns ( 55.05 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.434 ns ( 44.95 % ) " "Info: Total interconnect delay = 1.434 ns ( 44.95 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.190 ns" { clk clk~clkctrl usb2_test:inst1|cnt2[6] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.190 ns" { clk {} clk~combout {} clk~clkctrl {} usb2_test:inst1|cnt2[6] {} } { 0.000ns 0.000ns 0.239ns 1.195ns } { 0.000ns 1.090ns 0.000ns 0.666ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.190 ns" { clk clk~clkctrl usb2_test:inst1|cnt2[4] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.190 ns" { clk {} clk~combout {} clk~clkctrl {} usb2_test:inst1|cnt2[4] {} } { 0.000ns 0.000ns 0.239ns 1.195ns } { 0.000ns 1.090ns 0.000ns 0.666ns } "" } } { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.190 ns" { clk clk~clkctrl usb2_test:inst1|cnt2[6] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.190 ns" { clk {} clk~combout {} clk~clkctrl {} usb2_test:inst1|cnt2[6] {} } { 0.000ns 0.000ns 0.239ns 1.195ns } { 0.000ns 1.090ns 0.000ns 0.666ns } "" } } } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.304 ns + " "Info: + Micro clock to output delay of source is 0.304 ns" { } { { "usb2_test.v" "" { Text "E:/wt/workspace/mywork/USB2_V/usb2_test.v" 34 -1 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.040 ns + " "Info: + Micro setup delay of destination is -0.040 ns" { } { { "usb2_test.v" "" { Text "E:/wt/workspace/mywork/USB2_V/usb2_test.v" 34 -1 0 } } } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0} } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.609 ns" { usb2_test:inst1|cnt2[6] usb2_test:inst1|Equal0~146 usb2_test:inst1|Equal0~149 usb2_test:inst1|Equal0~150 usb2_test:inst1|cnt2[4] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "4.609 ns" { usb2_test:inst1|cnt2[6] {} usb2_test:inst1|Equal0~146 {} usb2_test:inst1|Equal0~149 {} usb2_test:inst1|Equal0~150 {} usb2_test:inst1|cnt2[4] {} } { 0.000ns 1.092ns 0.368ns 0.380ns 0.542ns } { 0.000ns 0.577ns 0.589ns 0.206ns 0.855ns } "" } } { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.190 ns" { clk clk~clkctrl usb2_test:inst1|cnt2[4] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.190 ns" { clk {} clk~combout {} clk~clkctrl {} usb2_test:inst1|cnt2[4] {} } { 0.000ns 0.000ns 0.239ns 1.195ns } { 0.000ns 1.090ns 0.000ns 0.666ns } "" } } { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.190 ns" { clk clk~clkctrl usb2_test:inst1|cnt2[6] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.190 ns" { clk {} clk~combout {} clk~clkctrl {} usb2_test:inst1|cnt2[6] {} } { 0.000ns 0.000ns 0.239ns 1.195ns } { 0.000ns 1.090ns 0.000ns 0.666ns } "" } } } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0 "" 0}
{ "Info" "ITDB_TSU_RESULT" "usb2_test:inst1\|step.01 reset clk 1.383 ns register " "Info: tsu for register \"usb2_test:inst1\|step.01\" (data pin = \"reset\", clock pin = \"clk\") is 1.383 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.614 ns + Longest pin register " "Info: + Longest pin to register delay is 4.614 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.080 ns) 1.080 ns reset 1 PIN PIN_U12 2 " "Info: 1: + IC(0.000 ns) + CELL(1.080 ns) = 1.080 ns; Loc. = PIN_U12; Fanout = 2; PIN Node = 'reset'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { reset } "NODE_NAME" } } { "USB2_V.bdf" "" { Schematic "E:/wt/workspace/mywork/USB2_V/USB2_V.bdf" { { 280 -112 56 296 "reset" "" } { 152 248 312 168 "reset" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.803 ns) + CELL(0.623 ns) 4.506 ns usb2_test:inst1\|step.01~17 2 COMB LCCOMB_X60_Y22_N30 1 " "Info: 2: + IC(2.803 ns) + CELL(0.623 ns) = 4.506 ns; Loc. = LCCOMB_X60_Y22_N30; Fanout = 1; COMB Node = 'usb2_test:inst1\|step.01~17'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.426 ns" { reset usb2_test:inst1|step.01~17 } "NODE_NAME" } } { "usb2_test.v" "" { Text "E:/wt/workspace/mywork/USB2_V/usb2_test.v" 17 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.108 ns) 4.614 ns usb2_test:inst1\|step.01 3 REG LCFF_X60_Y22_N31 18 " "Info: 3: + IC(0.000 ns) + CELL(0.108 ns) = 4.614 ns; Loc. = LCFF_X60_Y22_N31; Fanout = 18; REG Node = 'usb2_test:inst1\|step.01'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.108 ns" { usb2_test:inst1|step.01~17 usb2_test:inst1|step.01 } "NODE_NAME" } } { "usb2_test.v" "" { Text "E:/wt/workspace/mywork/USB2_V/usb2_test.v" 17 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.811 ns ( 39.25 % ) " "Info: Total cell delay = 1.811 ns ( 39.25 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.803 ns ( 60.75 % ) " "Info: Total interconnect delay = 2.803 ns ( 60.75 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.614 ns" { reset usb2_test:inst1|step.01~17 usb2_test:inst1|step.01 } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "4.614 ns" { reset {} reset~combout {} usb2_test:inst1|step.01~17 {} usb2_test:inst1|step.01 {} } { 0.000ns 0.000ns 2.803ns 0.000ns } { 0.000ns 1.080ns 0.623ns 0.108ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.040 ns + " "Info: + Micro setup delay of destination is -0.040 ns" { } { { "usb2_test.v" "" { Text "E:/wt/workspace/mywork/USB2_V/usb2_test.v" 17 -1 0 } } } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 3.191 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 3.191 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.090 ns) 1.090 ns clk 1 CLK PIN_L1 1 " "Info: 1: + IC(0.000 ns) + CELL(1.090 ns) = 1.090 ns; Loc. = PIN_L1; Fanout = 1; CLK Node = 'clk'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "USB2_V.bdf" "" { Schematic "E:/wt/workspace/mywork/USB2_V/USB2_V.bdf" { { 264 -112 56 280 "clk" "" } { 136 264 328 152 "clk" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.239 ns) + CELL(0.000 ns) 1.329 ns clk~clkctrl 2 COMB CLKCTRL_G2 35 " "Info: 2: + IC(0.239 ns) + CELL(0.000 ns) = 1.329 ns; Loc. = CLKCTRL_G2; Fanout = 35; COMB Node = 'clk~clkctrl'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.239 ns" { clk clk~clkctrl } "NODE_NAME" } } { "USB2_V.bdf" "" { Schematic "E:/wt/workspace/mywork/USB2_V/USB2_V.bdf" { { 264 -112 56 280 "clk" "" } { 136 264 328 152 "clk" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.196 ns) + CELL(0.666 ns) 3.191 ns usb2_test:inst1\|step.01 3 REG LCFF_X60_Y22_N31 18 " "Info: 3: + IC(1.196 ns) + CELL(0.666 ns) = 3.191 ns; Loc. = LCFF_X60_Y22_N31; Fanout = 18; REG Node = 'usb2_test:inst1\|step.01'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.862 ns" { clk~clkctrl usb2_test:inst1|step.01 } "NODE_NAME" } } { "usb2_test.v" "" { Text "E:/wt/workspace/mywork/USB2_V/usb2_test.v" 17 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.756 ns ( 55.03 % ) " "Info: Total cell delay = 1.756 ns ( 55.03 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.435 ns ( 44.97 % ) " "Info: Total interconnect delay = 1.435 ns ( 44.97 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.191 ns" { clk clk~clkctrl usb2_test:inst1|step.01 } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.191 ns" { clk {} clk~combout {} clk~clkctrl {} usb2_test:inst1|step.01 {} } { 0.000ns 0.000ns 0.239ns 1.196ns } { 0.000ns 1.090ns 0.000ns 0.666ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.614 ns" { reset usb2_test:inst1|step.01~17 usb2_test:inst1|step.01 } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "4.614 ns" { reset {} reset~combout {} usb2_test:inst1|step.01~17 {} usb2_test:inst1|step.01 {} } { 0.000ns 0.000ns 2.803ns 0.000ns } { 0.000ns 1.080ns 0.623ns 0.108ns } "" } } { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.191 ns" { clk clk~clkctrl usb2_test:inst1|step.01 } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.191 ns" { clk {} clk~combout {} clk~clkctrl {} usb2_test:inst1|step.01 {} } { 0.000ns 0.000ns 0.239ns 1.196ns } { 0.000ns 1.090ns 0.000ns 0.666ns } "" } } } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk fd\[1\] usb2_test:inst1\|dataout\[1\] 10.309 ns register " "Info: tco from clock \"clk\" to destination pin \"fd\[1\]\" through register \"usb2_test:inst1\|dataout\[1\]\" is 10.309 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 3.191 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 3.191 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.090 ns) 1.090 ns clk 1 CLK PIN_L1 1 " "Info: 1: + IC(0.000 ns) + CELL(1.090 ns) = 1.090 ns; Loc. = PIN_L1; Fanout = 1; CLK Node = 'clk'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "USB2_V.bdf" "" { Schematic "E:/wt/workspace/mywork/USB2_V/USB2_V.bdf" { { 264 -112 56 280 "clk" "" } { 136 264 328 152 "clk" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.239 ns) + CELL(0.000 ns) 1.329 ns clk~clkctrl 2 COMB CLKCTRL_G2 35 " "Info: 2: + IC(0.239 ns) + CELL(0.000 ns) = 1.329 ns; Loc. = CLKCTRL_G2; Fanout = 35; COMB Node = 'clk~clkctrl'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.239 ns" { clk clk~clkctrl } "NODE_NAME" } } { "USB2_V.bdf" "" { Schematic "E:/wt/workspace/mywork/USB2_V/USB2_V.bdf" { { 264 -112 56 280 "clk" "" } { 136 264 328 152 "clk" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.196 ns) + CELL(0.666 ns) 3.191 ns usb2_test:inst1\|dataout\[1\] 3 REG LCFF_X61_Y22_N3 3 " "Info: 3: + IC(1.196 ns) + CELL(0.666 ns) = 3.191 ns; Loc. = LCFF_X61_Y22_N3; Fanout = 3; REG Node = 'usb2_test:inst1\|dataout\[1\]'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.862 ns" { clk~clkctrl usb2_test:inst1|dataout[1] } "NODE_NAME" } } { "usb2_test.v" "" { Text "E:/wt/workspace/mywork/USB2_V/usb2_test.v" 73 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.756 ns ( 55.03 % ) " "Info: Total cell delay = 1.756 ns ( 55.03 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.435 ns ( 44.97 % ) " "Info: Total interconnect delay = 1.435 ns ( 44.97 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.191 ns" { clk clk~clkctrl usb2_test:inst1|dataout[1] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.191 ns" { clk {} clk~combout {} clk~clkctrl {} usb2_test:inst1|dataout[1] {} } { 0.000ns 0.000ns 0.239ns 1.196ns } { 0.000ns 1.090ns 0.000ns 0.666ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.304 ns + " "Info: + Micro clock to output delay of source is 0.304 ns" { } { { "usb2_test.v" "" { Text "E:/wt/workspace/mywork/USB2_V/usb2_test.v" 73 -1 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.814 ns + Longest register pin " "Info: + Longest register to pin delay is 6.814 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns usb2_test:inst1\|dataout\[1\] 1 REG LCFF_X61_Y22_N3 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X61_Y22_N3; Fanout = 3; REG Node = 'usb2_test:inst1\|dataout\[1\]'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { usb2_test:inst1|dataout[1] } "NODE_NAME" } } { "usb2_test.v" "" { Text "E:/wt/workspace/mywork/USB2_V/usb2_test.v" 73 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.588 ns) + CELL(3.226 ns) 6.814 ns fd\[1\] 2 PIN PIN_T16 0 " "Info: 2: + IC(3.588 ns) + CELL(3.226 ns) = 6.814 ns; Loc. = PIN_T16; Fanout = 0; PIN Node = 'fd\[1\]'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "6.814 ns" { usb2_test:inst1|dataout[1] fd[1] } "NODE_NAME" } } { "USB2_V.bdf" "" { Schematic "E:/wt/workspace/mywork/USB2_V/USB2_V.bdf" { { 248 568 744 264 "fd\[15..0\]" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.226 ns ( 47.34 % ) " "Info: Total cell delay = 3.226 ns ( 47.34 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.588 ns ( 52.66 % ) " "Info: Total interconnect delay = 3.588 ns ( 52.66 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "6.814 ns" { usb2_test:inst1|dataout[1] fd[1] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "6.814 ns" { usb2_test:inst1|dataout[1] {} fd[1] {} } { 0.000ns 3.588ns } { 0.000ns 3.226ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.191 ns" { clk clk~clkctrl usb2_test:inst1|dataout[1] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.191 ns" { clk {} clk~combout {} clk~clkctrl {} usb2_test:inst1|dataout[1] {} } { 0.000ns 0.000ns 0.239ns 1.196ns } { 0.000ns 1.090ns 0.000ns 0.666ns } "" } } { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "6.814 ns" { usb2_test:inst1|dataout[1] fd[1] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "6.814 ns" { usb2_test:inst1|dataout[1] {} fd[1] {} } { 0.000ns 3.588ns } { 0.000ns 3.226ns } "" } } } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0}
{ "Info" "ITDB_TH_RESULT" "usb2_test:inst1\|step.01 reset clk -1.117 ns register " "Info: th for register \"usb2_test:inst1\|step.01\" (data pin = \"reset\", clock pin = \"clk\") is -1.117 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 3.191 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 3.191 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.090 ns) 1.090 ns clk 1 CLK PIN_L1 1 " "Info: 1: + IC(0.000 ns) + CELL(1.090 ns) = 1.090 ns; Loc. = PIN_L1; Fanout = 1; CLK Node = 'clk'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "USB2_V.bdf" "" { Schematic "E:/wt/workspace/mywork/USB2_V/USB2_V.bdf" { { 264 -112 56 280 "clk" "" } { 136 264 328 152 "clk" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.239 ns) + CELL(0.000 ns) 1.329 ns clk~clkctrl 2 COMB CLKCTRL_G2 35 " "Info: 2: + IC(0.239 ns) + CELL(0.000 ns) = 1.329 ns; Loc. = CLKCTRL_G2; Fanout = 35; COMB Node = 'clk~clkctrl'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.239 ns" { clk clk~clkctrl } "NODE_NAME" } } { "USB2_V.bdf" "" { Schematic "E:/wt/workspace/mywork/USB2_V/USB2_V.bdf" { { 264 -112 56 280 "clk" "" } { 136 264 328 152 "clk" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.196 ns) + CELL(0.666 ns) 3.191 ns usb2_test:inst1\|step.01 3 REG LCFF_X60_Y22_N31 18 " "Info: 3: + IC(1.196 ns) + CELL(0.666 ns) = 3.191 ns; Loc. = LCFF_X60_Y22_N31; Fanout = 18; REG Node = 'usb2_test:inst1\|step.01'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.862 ns" { clk~clkctrl usb2_test:inst1|step.01 } "NODE_NAME" } } { "usb2_test.v" "" { Text "E:/wt/workspace/mywork/USB2_V/usb2_test.v" 17 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.756 ns ( 55.03 % ) " "Info: Total cell delay = 1.756 ns ( 55.03 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.435 ns ( 44.97 % ) " "Info: Total interconnect delay = 1.435 ns ( 44.97 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.191 ns" { clk clk~clkctrl usb2_test:inst1|step.01 } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.191 ns" { clk {} clk~combout {} clk~clkctrl {} usb2_test:inst1|step.01 {} } { 0.000ns 0.000ns 0.239ns 1.196ns } { 0.000ns 1.090ns 0.000ns 0.666ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TH_DELAY" "0.306 ns + " "Info: + Micro hold delay of destination is 0.306 ns" { } { { "usb2_test.v" "" { Text "E:/wt/workspace/mywork/USB2_V/usb2_test.v" 17 -1 0 } } } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.614 ns - Shortest pin register " "Info: - Shortest pin to register delay is 4.614 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.080 ns) 1.080 ns reset 1 PIN PIN_U12 2 " "Info: 1: + IC(0.000 ns) + CELL(1.080 ns) = 1.080 ns; Loc. = PIN_U12; Fanout = 2; PIN Node = 'reset'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { reset } "NODE_NAME" } } { "USB2_V.bdf" "" { Schematic "E:/wt/workspace/mywork/USB2_V/USB2_V.bdf" { { 280 -112 56 296 "reset" "" } { 152 248 312 168 "reset" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.803 ns) + CELL(0.623 ns) 4.506 ns usb2_test:inst1\|step.01~17 2 COMB LCCOMB_X60_Y22_N30 1 " "Info: 2: + IC(2.803 ns) + CELL(0.623 ns) = 4.506 ns; Loc. = LCCOMB_X60_Y22_N30; Fanout = 1; COMB Node = 'usb2_test:inst1\|step.01~17'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.426 ns" { reset usb2_test:inst1|step.01~17 } "NODE_NAME" } } { "usb2_test.v" "" { Text "E:/wt/workspace/mywork/USB2_V/usb2_test.v" 17 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.108 ns) 4.614 ns usb2_test:inst1\|step.01 3 REG LCFF_X60_Y22_N31 18 " "Info: 3: + IC(0.000 ns) + CELL(0.108 ns) = 4.614 ns; Loc. = LCFF_X60_Y22_N31; Fanout = 18; REG Node = 'usb2_test:inst1\|step.01'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.108 ns" { usb2_test:inst1|step.01~17 usb2_test:inst1|step.01 } "NODE_NAME" } } { "usb2_test.v" "" { Text "E:/wt/workspace/mywork/USB2_V/usb2_test.v" 17 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.811 ns ( 39.25 % ) " "Info: Total cell delay = 1.811 ns ( 39.25 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.803 ns ( 60.75 % ) " "Info: Total interconnect delay = 2.803 ns ( 60.75 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.614 ns" { reset usb2_test:inst1|step.01~17 usb2_test:inst1|step.01 } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "4.614 ns" { reset {} reset~combout {} usb2_test:inst1|step.01~17 {} usb2_test:inst1|step.01 {} } { 0.000ns 0.000ns 2.803ns 0.000ns } { 0.000ns 1.080ns 0.623ns 0.108ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.191 ns" { clk clk~clkctrl usb2_test:inst1|step.01 } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.191 ns" { clk {} clk~combout {} clk~clkctrl {} usb2_test:inst1|step.01 {} } { 0.000ns 0.000ns 0.239ns 1.196ns } { 0.000ns 1.090ns 0.000ns 0.666ns } "" } } { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.614 ns" { reset usb2_test:inst1|step.01~17 usb2_test:inst1|step.01 } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "4.614 ns" { reset {} reset~combout {} usb2_test:inst1|step.01~17 {} usb2_test:inst1|step.01 {} } { 0.000ns 0.000ns 2.803ns 0.000ns } { 0.000ns 1.080ns 0.623ns 0.108ns } "" } } } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}
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