usb2_v.map.qmsg

USB2_V例子工程是一个FPGA数据通过USB2.0传输到PC机的示例.

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.2 Build 207 03/18/2008 Service Pack 3 SJ Full Version " "Info: Version 7.2 Build 207 03/18/2008 Service Pack 3 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0} { "Info" "IQEXE_START_BANNER_TIME" "Mon May 18 11:47:32 2009 " "Info: Processing started: Mon May 18 11:47:32 2009" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off USB2_V -c USB2_V " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off USB2_V -c USB2_V" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "USB2_V.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file USB2_V.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 USB2_V " "Info: Found entity 1: USB2_V" {  } { { "USB2_V.bdf" "" { Schematic "E:/wt/workspace/mywork/USB2_V/USB2_V.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "usb_port.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file usb_port.v" { { "Info" "ISGN_ENTITY_NAME" "1 usb_port " "Info: Found entity 1: usb_port" {  } { { "usb_port.v" "" { Text "E:/wt/workspace/mywork/USB2_V/usb_port.v" 4 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "usb2_test.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file usb2_test.v" { { "Info" "ISGN_ENTITY_NAME" "1 usb2_test " "Info: Found entity 1: usb2_test" {  } { { "usb2_test.v" "" { Text "E:/wt/workspace/mywork/USB2_V/usb2_test.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "USB2_V " "Info: Elaborating entity \"USB2_V\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "usb_port usb_port:inst " "Info: Elaborating entity \"usb_port\" for hierarchy \"usb_port:inst\"" {  } { { "USB2_V.bdf" "inst" { Schematic "E:/wt/workspace/mywork/USB2_V/USB2_V.bdf" { { 192 368 568 384 "inst" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "data usb_port.v(45) " "Warning (10036): Verilog HDL or VHDL warning at usb_port.v(45): object \"data\" assigned a value but never read" {  } { { "usb_port.v" "" { Text "E:/wt/workspace/mywork/USB2_V/usb_port.v" 45 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "" 0}
{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "state usb_port.v(49) " "Warning (10036): Verilog HDL or VHDL warning at usb_port.v(49): object \"state\" assigned a value but never read" {  } { { "usb_port.v" "" { Text "E:/wt/workspace/mywork/USB2_V/usb_port.v" 49 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "" 0}
{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "FD_EN usb_port.v(58) " "Warning (10036): Verilog HDL or VHDL warning at usb_port.v(58): object \"FD_EN\" assigned a value but never read" {  } { { "usb_port.v" "" { Text "E:/wt/workspace/mywork/USB2_V/usb_port.v" 58 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "sloe_n usb_port.v(87) " "Warning (10240): Verilog HDL Always Construct warning at usb_port.v(87): inferring latch(es) for variable \"sloe_n\", which holds its previous value in one or more paths through the always construct" {  } { { "usb_port.v" "" { Text "E:/wt/workspace/mywork/USB2_V/usb_port.v" 87 0 0 } }  } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "slrd_n usb_port.v(87) " "Warning (10240): Verilog HDL Always Construct warning at usb_port.v(87): inferring latch(es) for variable \"slrd_n\", which holds its previous value in one or more paths through the always construct" {  } { { "usb_port.v" "" { Text "E:/wt/workspace/mywork/USB2_V/usb_port.v" 87 0 0 } }  } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "write_done usb_port.v(87) " "Warning (10240): Verilog HDL Always Construct warning at usb_port.v(87): inferring latch(es) for variable \"write_done\", which holds its previous value in one or more paths through the always construct" {  } { { "usb_port.v" "" { Text "E:/wt/workspace/mywork/USB2_V/usb_port.v" 87 0 0 } }  } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "read_done usb_port.v(87) " "Warning (10240): Verilog HDL Always Construct warning at usb_port.v(87): inferring latch(es) for variable \"read_done\", which holds its previous value in one or more paths through the always construct" {  } { { "usb_port.v" "" { Text "E:/wt/workspace/mywork/USB2_V/usb_port.v" 87 0 0 } }  } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "readdata usb_port.v(87) " "Warning (10240): Verilog HDL Always Construct warning at usb_port.v(87): inferring latch(es) for variable \"readdata\", which holds its previous value in one or more paths through the always construct" {  } { { "usb_port.v" "" { Text "E:/wt/workspace/mywork/USB2_V/usb_port.v" 87 0 0 } }  } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "readdata\[0\] usb_port.v(87) " "Info (10041): Inferred latch for \"readdata\[0\]\" at usb_port.v(87)" {  } { { "usb_port.v" "" { Text "E:/wt/workspace/mywork/USB2_V/usb_port.v" 87 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "readdata\[1\] usb_port.v(87) " "Info (10041): Inferred latch for \"readdata\[1\]\" at usb_port.v(87)" {  } { { "usb_port.v" "" { Text "E:/wt/workspace/mywork/USB2_V/usb_port.v" 87 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "readdata\[2\] usb_port.v(87) " "Info (10041): Inferred latch for \"readdata\[2\]\" at usb_port.v(87)" {  } { { "usb_port.v" "" { Text "E:/wt/workspace/mywork/USB2_V/usb_port.v" 87 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "readdata\[3\] usb_port.v(87) " "Info (10041): Inferred latch for \"readdata\[3\]\" at usb_port.v(87)" {  } { { "usb_port.v" "" { Text "E:/wt/workspace/mywork/USB2_V/usb_port.v" 87 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "readdata\[4\] usb_port.v(87) " "Info (10041): Inferred latch for \"readdata\[4\]\" at usb_port.v(87)" {  } { { "usb_port.v" "" { Text "E:/wt/workspace/mywork/USB2_V/usb_port.v" 87 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "readdata\[5\] usb_port.v(87) " "Info (10041): Inferred latch for \"readdata\[5\]\" at usb_port.v(87)" {  } { { "usb_port.v" "" { Text "E:/wt/workspace/mywork/USB2_V/usb_port.v" 87 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "readdata\[6\] usb_port.v(87) " "Info (10041): Inferred latch for \"readdata\[6\]\" at usb_port.v(87)" {  } { { "usb_port.v" "" { Text "E:/wt/workspace/mywork/USB2_V/usb_port.v" 87 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "readdata\[7\] usb_port.v(87) " "Info (10041): Inferred latch for \"readdata\[7\]\" at usb_port.v(87)" {  } { { "usb_port.v" "" { Text "E:/wt/workspace/mywork/USB2_V/usb_port.v" 87 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "readdata\[8\] usb_port.v(87) " "Info (10041): Inferred latch for \"readdata\[8\]\" at usb_port.v(87)" {  } { { "usb_port.v" "" { Text "E:/wt/workspace/mywork/USB2_V/usb_port.v" 87 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "readdata\[9\] usb_port.v(87) " "Info (10041): Inferred latch for \"readdata\[9\]\" at usb_port.v(87)" {  } { { "usb_port.v" "" { Text "E:/wt/workspace/mywork/USB2_V/usb_port.v" 87 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "readdata\[10\] usb_port.v(87) " "Info (10041): Inferred latch for \"readdata\[10\]\" at usb_port.v(87)" {  } { { "usb_port.v" "" { Text "E:/wt/workspace/mywork/USB2_V/usb_port.v" 87 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "readdata\[11\] usb_port.v(87) " "Info (10041): Inferred latch for \"readdata\[11\]\" at usb_port.v(87)" {  } { { "usb_port.v" "" { Text "E:/wt/workspace/mywork/USB2_V/usb_port.v" 87 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "readdata\[12\] usb_port.v(87) " "Info (10041): Inferred latch for \"readdata\[12\]\" at usb_port.v(87)" {  } { { "usb_port.v" "" { Text "E:/wt/workspace/mywork/USB2_V/usb_port.v" 87 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "readdata\[13\] usb_port.v(87) " "Info (10041): Inferred latch for \"readdata\[13\]\" at usb_port.v(87)" {  } { { "usb_port.v" "" { Text "E:/wt/workspace/mywork/USB2_V/usb_port.v" 87 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "readdata\[14\] usb_port.v(87) " "Info (10041): Inferred latch for \"readdata\[14\]\" at usb_port.v(87)" {  } { { "usb_port.v" "" { Text "E:/wt/workspace/mywork/USB2_V/usb_port.v" 87 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "readdata\[15\] usb_port.v(87) " "Info (10041): Inferred latch for \"readdata\[15\]\" at usb_port.v(87)" {  } { { "usb_port.v" "" { Text "E:/wt/workspace/mywork/USB2_V/usb_port.v" 87 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "read_done usb_port.v(87) " "Info (10041): Inferred latch for \"read_done\" at usb_port.v(87)" {  } { { "usb_port.v" "" { Text "E:/wt/workspace/mywork/USB2_V/usb_port.v" 87 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "write_done usb_port.v(87) " "Info (10041): Inferred latch for \"write_done\" at usb_port.v(87)" {  } { { "usb_port.v" "" { Text "E:/wt/workspace/mywork/USB2_V/usb_port.v" 87 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}