usb2_v.fit.qmsg

USB2_V例子工程是一个FPGA数据通过USB2.0传输到PC机的示例.

{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Info: Fitter placement preparation operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Info: Fitter placement operations beginning" {  } {  } 0 0 "Fitter placement operations beginning" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" {  } {  } 0 0 "Fitter placement was successful" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Info: Fitter placement operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "" 0}
{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "4.336 ns register register " "Info: Estimated most critical path is register to register delay of 4.336 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns usb2_test:inst1\|cnt2\[14\] 1 REG LAB_X59_Y22 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X59_Y22; Fanout = 3; REG Node = 'usb2_test:inst1\|cnt2\[14\]'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { usb2_test:inst1|cnt2[14] } "NODE_NAME" } } { "usb2_test.v" "" { Text "E:/wt/workspace/mywork/USB2_V/usb2_test.v" 34 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.981 ns) + CELL(0.206 ns) 1.187 ns usb2_test:inst1\|Equal0~148 2 COMB LAB_X60_Y22 1 " "Info: 2: + IC(0.981 ns) + CELL(0.206 ns) = 1.187 ns; Loc. = LAB_X60_Y22; Fanout = 1; COMB Node = 'usb2_test:inst1\|Equal0~148'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.187 ns" { usb2_test:inst1|cnt2[14] usb2_test:inst1|Equal0~148 } "NODE_NAME" } } { "usb2_test.v" "" { Text "E:/wt/workspace/mywork/USB2_V/usb2_test.v" 28 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.606 ns) + CELL(0.206 ns) 1.999 ns usb2_test:inst1\|Equal0~149 3 COMB LAB_X60_Y22 2 " "Info: 3: + IC(0.606 ns) + CELL(0.206 ns) = 1.999 ns; Loc. = LAB_X60_Y22; Fanout = 2; COMB Node = 'usb2_test:inst1\|Equal0~149'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.812 ns" { usb2_test:inst1|Equal0~148 usb2_test:inst1|Equal0~149 } "NODE_NAME" } } { "usb2_test.v" "" { Text "E:/wt/workspace/mywork/USB2_V/usb2_test.v" 28 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.161 ns) + CELL(0.651 ns) 2.811 ns usb2_test:inst1\|Equal0~150 4 COMB LAB_X60_Y22 16 " "Info: 4: + IC(0.161 ns) + CELL(0.651 ns) = 2.811 ns; Loc. = LAB_X60_Y22; Fanout = 16; COMB Node = 'usb2_test:inst1\|Equal0~150'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.812 ns" { usb2_test:inst1|Equal0~149 usb2_test:inst1|Equal0~150 } "NODE_NAME" } } { "usb2_test.v" "" { Text "E:/wt/workspace/mywork/USB2_V/usb2_test.v" 28 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.670 ns) + CELL(0.855 ns) 4.336 ns usb2_test:inst1\|cnt2\[4\] 5 REG LAB_X59_Y22 3 " "Info: 5: + IC(0.670 ns) + CELL(0.855 ns) = 4.336 ns; Loc. = LAB_X59_Y22; Fanout = 3; REG Node = 'usb2_test:inst1\|cnt2\[4\]'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.525 ns" { usb2_test:inst1|Equal0~150 usb2_test:inst1|cnt2[4] } "NODE_NAME" } } { "usb2_test.v" "" { Text "E:/wt/workspace/mywork/USB2_V/usb2_test.v" 34 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.918 ns ( 44.23 % ) " "Info: Total cell delay = 1.918 ns ( 44.23 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.418 ns ( 55.77 % ) " "Info: Total interconnect delay = 2.418 ns ( 55.77 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.336 ns" { usb2_test:inst1|cnt2[14] usb2_test:inst1|Equal0~148 usb2_test:inst1|Equal0~149 usb2_test:inst1|Equal0~150 usb2_test:inst1|cnt2[4] } "NODE_NAME" } }  } 0 0 "Estimated most critical path is %2!s! to %3!s! delay of %1!s!" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" {  } {  } 0 0 "Fitter routing operations beginning" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 " "Info: Average interconnect usage is 0% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "0 X55_Y24 X65_Y36 " "Info: Peak interconnect usage is 0% of the available device resources in the region that extends from location X55_Y24 to location X65_Y36" {  } {  } 0 0 "Peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "" 0}  } {  } 0 0 "Average interconnect usage is %1!d!%% of the available device resources" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Info: Fitter routing operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "" 0}