usb2_test.v.bak

USB2_V例子工程是一个FPGA数据通过USB2.0传输到PC机的示例.

module usb2_test(clk,reset,write_n,dataout,done_in);

input   clk;
input   reset;
input   done_in;
output [15:0] dataout;
output  write_n;


reg     write_n_r;
reg     done_in_pre;
reg     done_in_now;
reg [15:0] cnt2;

reg [15:0] dataout;
reg    start;
reg [1:0] step;

/*延时一段时间开始*/       
always @(posedge clk or negedge reset)
   if(!reset)
   begin
    cnt2 <= 0;
    start <= 1'b1;
    end
    else
    begin
     if (cnt2 !=16'hfffe)
       cnt2 <= cnt2 +1'b1;
     if(cnt2 == 16'hfff0) //给 start一个低脉冲启动写传输
      start <= 1'b0; 
      else
       start <= 1'b1;
    end

assign  write_n = start  &  write_n_r ;


always @(posedge clk or negedge reset)
if(!reset)
begin
 dataout <= 16'h0000;
 write_n_r <= 1;
 done_in_pre <= 0;
 done_in_now<= 0;
 end
 else
// begin
//   done_in_pre <= done_in_now;
//   done_in_now <= done_in;
//   if({done_in_pre,done_in_now}==2'b01)
//    begin
//      dataout <= dataout + 1'b1;
//      write_n_r <= 0;
//     end
//    else
//      write_n_r <= 1;
// end
 begin
	case(step)
	0:
	  begin
		dataout <= dataout + 1'b1;
		write_n_r <= 0;
		step <= 1;
	  end
	1:
	  begin
		write_n_r <= 1;
		step <=2;
	  end
	2:step <=0;
	endcase
 end
 
endmodule