jtag.map.rpt

altera usb下载线原理图和cpld程序

; Analysis & Synthesis Resource Usage Summary            ;
+---------------------------------------------+----------+
; Resource                                    ; Usage    ;
+---------------------------------------------+----------+
; Total logic elements                        ; 70       ;
;     -- Combinational with no register       ; 32       ;
;     -- Register only                        ; 10       ;
;     -- Combinational with a register        ; 28       ;
;                                             ;          ;
; Logic element usage by number of LUT inputs ;          ;
;     -- 4 input functions                    ; 31       ;
;     -- 3 input functions                    ; 18       ;
;     -- 2 input functions                    ; 10       ;
;     -- 1 input functions                    ; 1        ;
;     -- 0 input functions                    ; 0        ;
;                                             ;          ;
; Logic elements by mode                      ;          ;
;     -- normal mode                          ; 62       ;
;     -- arithmetic mode                      ; 8        ;
;     -- qfbk mode                            ; 0        ;
;     -- register cascade mode                ; 0        ;
;     -- synchronous clear/load mode          ; 10       ;
;     -- asynchronous clear/load mode         ; 0        ;
;                                             ;          ;
; Total registers                             ; 38       ;
; Total logic cells in carry chains           ; 9        ;
; I/O pins                                    ; 17       ;
; Maximum fan-out node                        ; CLK12MHz ;
; Maximum fan-out                             ; 38       ;
; Total fan-out                               ; 303      ;
; Average fan-out                             ; 3.48     ;
+---------------------------------------------+----------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                                      ;
+----------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+------------------------+
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; UFM Blocks ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name    ;
+----------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+------------------------+
; |JTAG                      ; 70 (0)      ; 38           ; 0          ; 17   ; 0            ; 32 (0)       ; 10 (0)            ; 28 (0)           ; 9 (0)           ; 0 (0)      ; |JTAG                  ;
;    |jtag_logic:inst6|      ; 70 (70)     ; 38           ; 0          ; 0    ; 0            ; 32 (32)      ; 10 (10)           ; 28 (28)          ; 9 (9)           ; 0 (0)      ; |JTAG|jtag_logic:inst6 ;
+----------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+------------------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+-------------------------------------------------------------------+
; Registers Removed During Synthesis                                ;
+---------------------------------------+---------------------------+
; Register name                         ; Reason for Removal        ;
+---------------------------------------+---------------------------+
; inst6/D[1]~en                         ; Merged with inst6/D[0]~en ;
; inst6/D[2]~en                         ; Merged with inst6/D[0]~en ;
; inst6/D[3]~en                         ; Merged with inst6/D[0]~en ;
; inst6/D[4]~en                         ; Merged with inst6/D[0]~en ;
; inst6/D[5]~en                         ; Merged with inst6/D[0]~en ;
; inst6/D[6]~en                         ; Merged with inst6/D[0]~en ;
; inst6/D[7]~en                         ; Merged with inst6/D[0]~en ;
; Total Number of Removed Registers = 7 ;                           ;
+---------------------------------------+---------------------------+


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 38    ;
; Number of registers using Synchronous Clear  ; 0     ;
; Number of registers using Synchronous Load   ; 10    ;
; Number of registers using Asynchronous Clear ; 0     ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 18    ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+---------------------------------------------------------------------------------------------------------------------------------------------------+
; Multiplexer Restructuring Statistics (Restructuring Performed)                                                                                    ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+-------------------------------------+
; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output          ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+-------------------------------------+
; 3:1                ; 3 bits    ; 6 LEs         ; 3 LEs                ; 3 LEs                  ; Yes        ; |JTAG|jtag_logic:inst6|bitcount[0]  ;
; 3:1                ; 6 bits    ; 12 LEs        ; 6 LEs                ; 6 LEs                  ; Yes        ; |JTAG|jtag_logic:inst6|bitcount[3]  ;
; 4:1                ; 7 bits    ; 14 LEs        ; 14 LEs               ; 0 LEs                  ; Yes        ; |JTAG|jtag_logic:inst6|ioshifter[1] ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+-------------------------------------+


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 7.0 Build 33 02/05/2007 SJ Full Version
    Info: Processing started: Wed Jun 13 16:24:26 2007
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off JTAG -c JTAG
Info: Found 1 design units, including 1 entities, in source file JTAG.bdf
    Info: Found entity 1: JTAG
Info: Found 2 design units, including 1 entities, in source file jtag_logic.vhd
    Info: Found design unit 1: jtag_logic-spec
    Info: Found entity 1: jtag_logic
Info: Elaborating entity "JTAG" for the top level hierarchy
Info: Elaborating entity "jtag_logic" for hierarchy "jtag_logic:inst6"
Info: Duplicate registers merged to single register
    Info: Duplicate register "jtag_logic:inst6|D[1]~en" merged to single register "jtag_logic:inst6|D[0]~en"
    Info: Duplicate register "jtag_logic:inst6|D[2]~en" merged to single register "jtag_logic:inst6|D[0]~en"
    Info: Duplicate register "jtag_logic:inst6|D[3]~en" merged to single register "jtag_logic:inst6|D[0]~en"
    Info: Duplicate register "jtag_logic:inst6|D[4]~en" merged to single register "jtag_logic:inst6|D[0]~en"
    Info: Duplicate register "jtag_logic:inst6|D[5]~en" merged to single register "jtag_logic:inst6|D[0]~en"
    Info: Duplicate register "jtag_logic:inst6|D[6]~en" merged to single register "jtag_logic:inst6|D[0]~en"
    Info: Duplicate register "jtag_logic:inst6|D[7]~en" merged to single register "jtag_logic:inst6|D[0]~en"
Info: Implemented 87 device resources after synthesis - the final resource count might be different
    Info: Implemented 4 input pins
    Info: Implemented 5 output pins
    Info: Implemented 8 bidirectional pins
    Info: Implemented 70 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 0 warnings
    Info: Allocated 139 megabytes of memory during processing
    Info: Processing ended: Wed Jun 13 16:24:30 2007
    Info: Elapsed time: 00:00:04