jtag.fit.smsg

altera usb下载线原理图和cpld程序

Info: *******************************************************************
Info: Running Quartus II Fitter
    Info: Version 7.0 Build 33 02/05/2007 SJ Full Version
    Info: Processing started: Wed Jun 13 16:24:31 2007
Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off JTAG -c JTAG
Info: Selected device EPM240T100C5 for design "JTAG"
Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time
Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices
    Info: Device EPM240T100I5 is compatible
    Info: Device EPM570T100C5 is compatible
    Info: Device EPM570T100I5 is compatible
Info: Fitter is using the Classic Timing Analyzer
Info: Timing requirements not specified -- optimizing circuit to achieve the following default global requirements
    Info: Assuming a global fmax requirement of 1000 MHz
    Info: Assuming a global tsu requirement of 2.0 ns
    Info: Assuming a global tco requirement of 1.0 ns
    Info: Assuming a global tpd requirement of 1.0 ns
Info: Completed User Assigned Global Signals Promotion Operation
Info: Automatically promoted signal "CLK12MHz" to use Global clock in PIN 12
Info: Completed Auto Global Promotion Operation
Info: Starting register packing
Info: Fitter is using Normal packing mode for logic elements with Auto setting for Auto Packed Registers logic option
Info: Started processing fast register assignments
Info: Finished processing fast register assignments
Info: Finished register packing: elapsed time is 00:00:00
Info: Fitter placement preparation operations beginning
Info: Fitter placement preparation operations ending: elapsed time is 00:00:00
Info: Fitter placement operations beginning
Info: Fitter placement was successful
Info: Fitter placement operations ending: elapsed time is 00:00:00
Info: Estimated most critical path is register to pin delay of 4.620 ns
    Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X5_Y1; Fanout = 2; REG Node = 'jtag_logic:inst6|B_TCK'
    Info: 2: + IC(2.298 ns) + CELL(2.322 ns) = 4.620 ns; Loc. = PIN_2; Fanout = 0; PIN Node = 'TCK1'
    Info: Total cell delay = 2.322 ns ( 50.26 % )
    Info: Total interconnect delay = 2.298 ns ( 49.74 % )
Info: Fitter routing operations beginning
Info: Average interconnect usage is 7% of the available device resources. Peak interconnect usage is 7%
    Info: The peak interconnect region extends from location X0_Y0 to location X8_Y5
Info: Fitter routing operations ending: elapsed time is 00:00:00
Info: The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time.
    Info: Optimizations that may affect the design's routability were skipped
    Info: Optimizations that may affect the design's timing were skipped
Info: Following groups of pins have the same output enable
    Info: Following pins have the same output enable: jtag_logic:inst6|D[0]~en
        Info: Type bidirectional pin FD[6] uses the 3.3-V LVTTL I/O standard
        Info: Type bidirectional pin FD[4] uses the 3.3-V LVTTL I/O standard
        Info: Type bidirectional pin FD[2] uses the 3.3-V LVTTL I/O standard
        Info: Type bidirectional pin FD[0] uses the 3.3-V LVTTL I/O standard
        Info: Type bidirectional pin FD[7] uses the 3.3-V LVTTL I/O standard
        Info: Type bidirectional pin FD[5] uses the 3.3-V LVTTL I/O standard
        Info: Type bidirectional pin FD[3] uses the 3.3-V LVTTL I/O standard
        Info: Type bidirectional pin FD[1] uses the 3.3-V LVTTL I/O standard
Info: Quartus II Fitter was successful. 0 errors, 0 warnings
    Info: Allocated 154 megabytes of memory during processing
    Info: Processing ended: Wed Jun 13 16:24:32 2007
    Info: Elapsed time: 00:00:01