usb2_v.map.rpt

USB2_V例子工程是一个FPGA数据通过USB2.0传输到PC机的示例.

Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


Encoding Type:  One-Hot
+----------------------------------------------+
; State Machine - |USB2_V|usb2_test:inst1|step ;
+---------+------------------------------------+
; Name    ; step.01                            ;
+---------+------------------------------------+
; step.00 ; 0                                  ;
; step.01 ; 1                                  ;
+---------+------------------------------------+


+------------------------------------------------------------+
; Registers Removed During Synthesis                         ;
+---------------------------------------+--------------------+
; Register name                         ; Reason for Removal ;
+---------------------------------------+--------------------+
; usb2_test:inst1|step~8                ; Lost fanout        ;
; Total Number of Removed Registers = 1 ;                    ;
+---------------------------------------+--------------------+


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 35    ;
; Number of registers using Synchronous Clear  ; 0     ;
; Number of registers using Synchronous Load   ; 0     ;
; Number of registers using Asynchronous Clear ; 34    ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 30    ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+--------------------------------------------------+
; Inverted Register Statistics                     ;
+----------------------------------------+---------+
; Inverted Register                      ; Fan out ;
+----------------------------------------+---------+
; usb2_test:inst1|start                  ; 1       ;
; usb2_test:inst1|write_n_r              ; 1       ;
; Total number of inverted registers = 2 ;         ;
+----------------------------------------+---------+


+------------------------------------------------------------+
; Parameter Settings for User Entity Instance: usb_port:inst ;
+----------------+-------+-----------------------------------+
; Parameter Name ; Value ; Type                              ;
+----------------+-------+-----------------------------------+
; R1             ; 000   ; Unsigned Binary                   ;
; R2             ; 001   ; Unsigned Binary                   ;
; R3             ; 011   ; Unsigned Binary                   ;
; W2             ; 010   ; Unsigned Binary                   ;
; W3             ; 110   ; Unsigned Binary                   ;
; W4             ; 100   ; Unsigned Binary                   ;
+----------------+-------+-----------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 7.2 Build 207 03/18/2008 Service Pack 3 SJ Full Version
    Info: Processing started: Mon May 18 11:47:32 2009
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off USB2_V -c USB2_V
Info: Found 1 design units, including 1 entities, in source file USB2_V.bdf
    Info: Found entity 1: USB2_V
Info: Found 1 design units, including 1 entities, in source file usb_port.v
    Info: Found entity 1: usb_port
Info: Found 1 design units, including 1 entities, in source file usb2_test.v
    Info: Found entity 1: usb2_test
Info: Elaborating entity "USB2_V" for the top level hierarchy
Info: Elaborating entity "usb_port" for hierarchy "usb_port:inst"
Warning (10036): Verilog HDL or VHDL warning at usb_port.v(45): object "data" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at usb_port.v(49): object "state" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at usb_port.v(58): object "FD_EN" assigned a value but never read
Warning (10240): Verilog HDL Always Construct warning at usb_port.v(87): inferring latch(es) for variable "sloe_n", which holds its previous value in one or more paths through the always construct
Warning (10240): Verilog HDL Always Construct warning at usb_port.v(87): inferring latch(es) for variable "slrd_n", which holds its previous value in one or more paths through the always construct
Warning (10240): Verilog HDL Always Construct warning at usb_port.v(87): inferring latch(es) for variable "write_done", which holds its previous value in one or more paths through the always construct
Warning (10240): Verilog HDL Always Construct warning at usb_port.v(87): inferring latch(es) for variable "read_done", which holds its previous value in one or more paths through the always construct
Warning (10240): Verilog HDL Always Construct warning at usb_port.v(87): inferring latch(es) for variable "readdata", which holds its previous value in one or more paths through the always construct
Info (10041): Inferred latch for "readdata[0]" at usb_port.v(87)
Info (10041): Inferred latch for "readdata[1]" at usb_port.v(87)
Info (10041): Inferred latch for "readdata[2]" at usb_port.v(87)
Info (10041): Inferred latch for "readdata[3]" at usb_port.v(87)
Info (10041): Inferred latch for "readdata[4]" at usb_port.v(87)
Info (10041): Inferred latch for "readdata[5]" at usb_port.v(87)
Info (10041): Inferred latch for "readdata[6]" at usb_port.v(87)
Info (10041): Inferred latch for "readdata[7]" at usb_port.v(87)
Info (10041): Inferred latch for "readdata[8]" at usb_port.v(87)
Info (10041): Inferred latch for "readdata[9]" at usb_port.v(87)
Info (10041): Inferred latch for "readdata[10]" at usb_port.v(87)
Info (10041): Inferred latch for "readdata[11]" at usb_port.v(87)
Info (10041): Inferred latch for "readdata[12]" at usb_port.v(87)
Info (10041): Inferred latch for "readdata[13]" at usb_port.v(87)
Info (10041): Inferred latch for "readdata[14]" at usb_port.v(87)
Info (10041): Inferred latch for "readdata[15]" at usb_port.v(87)
Info (10041): Inferred latch for "read_done" at usb_port.v(87)
Info (10041): Inferred latch for "write_done" at usb_port.v(87)
Info (10041): Inferred latch for "slrd_n" at usb_port.v(87)
Info (10041): Inferred latch for "sloe_n" at usb_port.v(87)
Info: Elaborating entity "usb2_test" for hierarchy "usb2_test:inst1"
Warning (10036): Verilog HDL or VHDL warning at usb2_test.v(11): object "done_in_pre" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at usb2_test.v(12): object "done_in_now" assigned a value but never read
Info: State machine "|USB2_V|usb2_test:inst1|step" contains 2 states
Info: Selected Auto state machine encoding method for state machine "|USB2_V|usb2_test:inst1|step"
Info: Encoding result for state machine "|USB2_V|usb2_test:inst1|step"
    Info: Completed encoding using 1 state bits
        Info: Encoded state bit "usb2_test:inst1|step.01"
    Info: State "|USB2_V|usb2_test:inst1|step.00" uses code string "0"
    Info: State "|USB2_V|usb2_test:inst1|step.01" uses code string "1"
Warning: Inserted an always-enabled tri-state buffer between logic and the tri-state bus fd~0 that it feeds
Warning: Inserted an always-enabled tri-state buffer between logic and the tri-state bus fd~1 that it feeds
Warning: Inserted an always-enabled tri-state buffer between logic and the tri-state bus fd~2 that it feeds
Warning: Inserted an always-enabled tri-state buffer between logic and the tri-state bus fd~3 that it feeds
Warning: Inserted an always-enabled tri-state buffer between logic and the tri-state bus fd~4 that it feeds
Warning: Inserted an always-enabled tri-state buffer between logic and the tri-state bus fd~5 that it feeds
Warning: Inserted an always-enabled tri-state buffer between logic and the tri-state bus fd~6 that it feeds
Warning: Inserted an always-enabled tri-state buffer between logic and the tri-state bus fd~7 that it feeds
Warning: Inserted an always-enabled tri-state buffer between logic and the tri-state bus fd~8 that it feeds
Warning: Inserted an always-enabled tri-state buffer between logic and the tri-state bus fd~9 that it feeds
Warning: Inserted an always-enabled tri-state buffer between logic and the tri-state bus fd~10 that it feeds
Warning: Inserted an always-enabled tri-state buffer between logic and the tri-state bus fd~11 that it feeds
Warning: Inserted an always-enabled tri-state buffer between logic and the tri-state bus fd~12 that it feeds
Warning: Inserted an always-enabled tri-state buffer between logic and the tri-state bus fd~13 that it feeds
Warning: Inserted an always-enabled tri-state buffer between logic and the tri-state bus fd~14 that it feeds
Warning: Inserted an always-enabled tri-state buffer between logic and the tri-state bus fd~15 that it feeds
Info: Registers with preset signals will power-up high
Info: DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back
Warning: TRI or OPNDRN buffers permanently enabled
    Warning: Node "fd~16"
    Warning: Node "fd~17"
    Warning: Node "fd~18"
    Warning: Node "fd~19"
    Warning: Node "fd~20"
    Warning: Node "fd~21"
    Warning: Node "fd~22"
    Warning: Node "fd~23"
    Warning: Node "fd~24"
    Warning: Node "fd~25"
    Warning: Node "fd~26"
    Warning: Node "fd~27"
    Warning: Node "fd~28"
    Warning: Node "fd~29"
    Warning: Node "fd~30"
    Warning: Node "fd~31"
Warning: Output pins are stuck at VCC or GND
    Warning (13410): Pin "sloe" stuck at VCC
    Warning (13410): Pin "slrd" stuck at VCC
    Warning (13410): Pin "PKTEND" stuck at VCC
    Warning (13410): Pin "fifoadr[1]" stuck at VCC
    Warning (13410): Pin "fifoadr[0]" stuck at VCC
Info: 1 registers lost all their fanouts during netlist optimizations. The first 1 are displayed below.
    Info: Register "usb2_test:inst1|step~8" lost all its fanouts during netlist optimizations.
Warning: Design contains 1 input pin(s) that do not drive logic
    Warning (15610): No output dependent on input pin "fifo_full"
Info: Implemented 66 device resources after synthesis - the final resource count might be different
    Info: Implemented 3 input pins
    Info: Implemented 6 output pins
    Info: Implemented 16 bidirectional pins
    Info: Implemented 41 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 51 warnings
    Info: Allocated 144 megabytes of memory during processing
    Info: Processing ended: Mon May 18 11:47:34 2009
    Info: Elapsed time: 00:00:02