usb_port.v.bak

USB2_V例子工程是一个FPGA数据通过USB2.0传输到PC机的示例.

`timescale 1ns / 1ps
// synthesis translate_on
module usb_port (
                   // inputs:
                      clk,
                      reset,
                      read_n,
                      write_n,
                      writedata,
                      fifo_full_n,
                      fifo_empty_n,

                   // outputs:
                      fifoadr,
                      slwr_n,
                      FD ,                 
                      readdata,
                      sloe_n,
                      slrd_n,
                      read_done,
                      write_done
                 )
;
    
    input             reset;
    output            slwr_n;
    output  [  1 : 0] fifoadr;
    inout   [  15: 0] FD;
    output            sloe_n;
    output            slrd_n;
    output  [ 15: 0 ] readdata;
    output            write_done;
    output            read_done;
    input             clk;
    input             fifo_empty_n;
    input             fifo_full_n;
    input             read_n;
    input               write_n;

    input     [  15: 0] writedata;

 //reg       [  15: 0] FD;

 reg      [ 15: 0 ]  data;
 reg      [ 15: 0 ]  readdata;
 reg                 slrd_n;
 reg                 sloe_n;
 reg        [2:0]    state;

 reg                 enable ;
 reg                 ctr_en ;
 reg                 fifo_adr;
 reg                 read_n_now;
 reg                 read_n_pre; 
 reg                 write_n_now;
 reg                 write_n_pre; 
 reg                 FD_EN;
 reg                 read_done;
 reg                 write_done;


 parameter R1=3'b000,R2=3'b001,R3=3'b011,W2=3'b010,W3=3'b110,W4=3'b100;


//assign readdata[15:0] = read_n ? 16'hzzzz : data[15:0];
assign FD[15:0] = writedata;
assign slwr_n = write_n;
assign fifoadr = 2'b11;

//always @(posedge clk or negedge reset)
//if(!reset)
//begin
// read_n_now  <= 0;
// read_n_pre   <= 0;
// write_n_now <= 0;
// write_n_pre  <= 0;
//end
//else
//  begin
//   read_n_pre <= read_n_now;
//   read_n_now <= read_n;
//   write_n_pre <= write_n_now;
//   write_n_now <= write_n;
//  end
  
always @(posedge clk or negedge reset)
 begin
 if(!reset)
  begin
   sloe_n <= 1'b1;
   slrd_n <= 1'b1;
   state <= R1;
   FD_EN <= 1'b0;
   write_done <= 1'b0;
   read_done <= 1'b0;
   readdata <= 16'h0000;
   data <= 16'h0000;
  end
//  else
//  case(state)
//    R1:
//       begin
//        if({read_n_pre,read_n_now} == 2'b10)
//         begin
//          fifoadr[1:0] <= 2'b00;//选择端点2用于in传输
//          sloe_n<=0;            //sloe=0，激活sloe
//          state <= R2;          //转向R2状态
//          FD_EN <= 1'b0;
//          read_done <= 1'b0;
//         end 
//         else if ({write_n_pre,write_n_now} == 2'b10)
//           begin
//           fifoadr[1:0] <= 2'b11;
//           state <= W2;
//           FD_EN <= 1'b0;
//           write_done <= 1'b0;
//           end
//       end
//    R2:
//      if(fifo_empty_n)     //如果fifo不空读数据，否则停在R2
//       begin
//         slrd_n<=0;       //slrd=0,激活slrd
//         readdata[15:0]<=FD[15:0];//传送总线采样数据
//         state<=R3;
//       end
//    R3:
//      begin
//       sloe_n<=1;//撒消sloe
//       slrd_n<=1;//撒消slrd
//       state<=R1;//回到状态R1
//       read_done <= 1'b1;
//      end
//    W2:
//       if(fifo_full_n)//如果fifo不满，开始写数据
//        begin
//         slwr_n<=0;//激活slwr
//         state<=W3;
//        end
//    W3:
//       begin
//    //   writedata <= writedata + 1'b1;
//       data<=writedata;//写入数据
//       state<=W4;
//       FD_EN <= 1'b1;
//       end
//    W4:
//     begin
//       slwr_n<=1;//撒消slwr
//       state<=R1;
//       write_done <= 1'b1;
//      end
//    default :  state<=R1;
//   endcase
  end



endmodule