clkdiv.vhd

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LIBRARY ieee;
USE ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

ENTITY clkdiv IS
PORT
(
	clk : IN STD_LOGIC;
	clk_2hz: out std_logic;
	clk_8hz: out std_logic		
);
	
END clkdiv;
ARCHITECTURE behave OF clkdiv IS
signal cnt:std_logic_vector(7 downto 0);	
BEGIN
process (clk)
begin
	if clk'event and clk='1' then
		cnt <= cnt + 1;
		clk_8hz <= cnt(1);
		clk_2hz <= cnt(4);
	end if;
end process;

END behave;