elevator.tan.qmsg

六层电梯控制vhdl六层电梯控制vhdl六层电梯控制vhdl六层电梯控制vhdl六层电梯控制vhdl

{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "2 " "Warning: Found 2 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "clkdiv:inst1\|clk_8hz " "Info: Detected ripple clock \"clkdiv:inst1\|clk_8hz\" as buffer" {  } { { "clkdiv.vhd" "" { Text "E:/project/elevator/clkdiv.vhd" 10 -1 0 } } { "d:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "clkdiv:inst1\|clk_8hz" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "clkdiv:inst1\|clk_2hz " "Info: Detected ripple clock \"clkdiv:inst1\|clk_2hz\" as buffer" {  } { { "clkdiv.vhd" "" { Text "E:/project/elevator/clkdiv.vhd" 9 -1 0 } } { "d:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "clkdiv:inst1\|clk_2hz" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0}  } {  } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0 "" 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register elerun:inst3\|one\[5\] register elerun:inst3\|udsig\[2\] 100.08 MHz 9.992 ns Internal " "Info: Clock \"clk\" has Internal fmax of 100.08 MHz between source register \"elerun:inst3\|one\[5\]\" and destination register \"elerun:inst3\|udsig\[2\]\" (period= 9.992 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "9.731 ns + Longest register register " "Info: + Longest register to register delay is 9.731 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns elerun:inst3\|one\[5\] 1 REG LC_X22_Y7_N8 9 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X22_Y7_N8; Fanout = 9; REG Node = 'elerun:inst3\|one\[5\]'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { elerun:inst3|one[5] } "NODE_NAME" } } { "elerun.vhd" "" { Text "E:/project/elevator/elerun.vhd" 213 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.282 ns) + CELL(0.442 ns) 1.724 ns elerun:inst3\|LessThan4~269 2 COMB LC_X21_Y6_N7 1 " "Info: 2: + IC(1.282 ns) + CELL(0.442 ns) = 1.724 ns; Loc. = LC_X21_Y6_N7; Fanout = 1; COMB Node = 'elerun:inst3\|LessThan4~269'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.724 ns" { elerun:inst3|one[5] elerun:inst3|LessThan4~269 } "NODE_NAME" } } { "d:/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "d:/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 1547 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.457 ns) + CELL(0.292 ns) 2.473 ns elerun:inst3\|LessThan4~271 3 COMB LC_X21_Y6_N3 1 " "Info: 3: + IC(0.457 ns) + CELL(0.292 ns) = 2.473 ns; Loc. = LC_X21_Y6_N3; Fanout = 1; COMB Node = 'elerun:inst3\|LessThan4~271'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.749 ns" { elerun:inst3|LessThan4~269 elerun:inst3|LessThan4~271 } "NODE_NAME" } } { "d:/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "d:/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 1547 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.238 ns) + CELL(0.114 ns) 3.825 ns elerun:inst3\|process0~954 4 COMB LC_X21_Y7_N7 1 " "Info: 4: + IC(1.238 ns) + CELL(0.114 ns) = 3.825 ns; Loc. = LC_X21_Y7_N7; Fanout = 1; COMB Node = 'elerun:inst3\|process0~954'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.352 ns" { elerun:inst3|LessThan4~271 elerun:inst3|process0~954 } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.209 ns) + CELL(0.114 ns) 5.148 ns elerun:inst3\|process0~963 5 COMB LC_X20_Y5_N8 3 " "Info: 5: + IC(1.209 ns) + CELL(0.114 ns) = 5.148 ns; Loc. = LC_X20_Y5_N8; Fanout = 3; COMB Node = 'elerun:inst3\|process0~963'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.323 ns" { elerun:inst3|process0~954 elerun:inst3|process0~963 } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.293 ns) + CELL(0.114 ns) 6.555 ns elerun:inst3\|Selector5~187 6 COMB LC_X19_Y6_N1 2 " "Info: 6: + IC(1.293 ns) + CELL(0.114 ns) = 6.555 ns; Loc. = LC_X19_Y6_N1; Fanout = 2; COMB Node = 'elerun:inst3\|Selector5~187'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.407 ns" { elerun:inst3|process0~963 elerun:inst3|Selector5~187 } "NODE_NAME" } } { "elerun.vhd" "" { Text "E:/project/elevator/elerun.vhd" 51 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.182 ns) + CELL(0.114 ns) 6.851 ns elerun:inst3\|udsig\[2\]~1014 7 COMB LC_X19_Y6_N2 1 " "Info: 7: + IC(0.182 ns) + CELL(0.114 ns) = 6.851 ns; Loc. = LC_X19_Y6_N2; Fanout = 1; COMB Node = 'elerun:inst3\|udsig\[2\]~1014'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.296 ns" { elerun:inst3|Selector5~187 elerun:inst3|udsig[2]~1014 } "NODE_NAME" } } { "elerun.vhd" "" { Text "E:/project/elevator/elerun.vhd" 50 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.449 ns) + CELL(0.292 ns) 7.592 ns elerun:inst3\|udsig\[2\]~1016 8 COMB LC_X19_Y6_N6 2 " "Info: 8: + IC(0.449 ns) + CELL(0.292 ns) = 7.592 ns; Loc. = LC_X19_Y6_N6; Fanout = 2; COMB Node = 'elerun:inst3\|udsig\[2\]~1016'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.741 ns" { elerun:inst3|udsig[2]~1014 elerun:inst3|udsig[2]~1016 } "NODE_NAME" } } { "elerun.vhd" "" { Text "E:/project/elevator/elerun.vhd" 50 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.272 ns) + CELL(0.867 ns) 9.731 ns elerun:inst3\|udsig\[2\] 9 REG LC_X20_Y8_N7 1 " "Info: 9: + IC(1.272 ns) + CELL(0.867 ns) = 9.731 ns; Loc. = LC_X20_Y8_N7; Fanout = 1; REG Node = 'elerun:inst3\|udsig\[2\]'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.139 ns" { elerun:inst3|udsig[2]~1016 elerun:inst3|udsig[2] } "NODE_NAME" } } { "elerun.vhd" "" { Text "E:/project/elevator/elerun.vhd" 50 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.349 ns ( 24.14 % ) " "Info: Total cell delay = 2.349 ns ( 24.14 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "7.382 ns ( 75.86 % ) " "Info: Total interconnect delay = 7.382 ns ( 75.86 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "9.731 ns" { elerun:inst3|one[5] elerun:inst3|LessThan4~269 elerun:inst3|LessThan4~271 elerun:inst3|process0~954 elerun:inst3|process0~963 elerun:inst3|Selector5~187 elerun:inst3|udsig[2]~1014 elerun:inst3|udsig[2]~1016 elerun:inst3|udsig[2] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "9.731 ns" { elerun:inst3|one[5] {} elerun:inst3|LessThan4~269 {} elerun:inst3|LessThan4~271 {} elerun:inst3|process0~954 {} elerun:inst3|process0~963 {} elerun:inst3|Selector5~187 {} elerun:inst3|udsig[2]~1014 {} elerun:inst3|udsig[2]~1016 {} elerun:inst3|udsig[2] {} } { 0.000ns 1.282ns 0.457ns 1.238ns 1.209ns 1.293ns 0.182ns 0.449ns 1.272ns } { 0.000ns 0.442ns 0.292ns 0.114ns 0.114ns 0.114ns 0.114ns 0.292ns 0.867ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 7.180 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 7.180 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_16 7 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_16; Fanout = 7; CLK Node = 'clk'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "elevator.bdf" "" { Schematic "E:/project/elevator/elevator.bdf" { { 192 64 232 208 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.560 ns) + CELL(0.935 ns) 2.964 ns clkdiv:inst1\|clk_2hz 2 REG LC_X8_Y6_N4 34 " "Info: 2: + IC(0.560 ns) + CELL(0.935 ns) = 2.964 ns; Loc. = LC_X8_Y6_N4; Fanout = 34; REG Node = 'clkdiv:inst1\|clk_2hz'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.495 ns" { clk clkdiv:inst1|clk_2hz } "NODE_NAME" } } { "clkdiv.vhd" "" { Text "E:/project/elevator/clkdiv.vhd" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.505 ns) + CELL(0.711 ns) 7.180 ns elerun:inst3\|udsig\[2\] 3 REG LC_X20_Y8_N7 1 " "Info: 3: + IC(3.505 ns) + CELL(0.711 ns) = 7.180 ns; Loc. = LC_X20_Y8_N7; Fanout = 1; REG Node = 'elerun:inst3\|udsig\[2\]'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.216 ns" { clkdiv:inst1|clk_2hz elerun:inst3|udsig[2] } "NODE_NAME" } } { "elerun.vhd" "" { Text "E:/project/elevator/elerun.vhd" 50 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.115 ns ( 43.38 % ) " "Info: Total cell delay = 3.115 ns ( 43.38 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.065 ns ( 56.62 % ) " "Info: Total interconnect delay = 4.065 ns ( 56.62 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "7.180 ns" { clk clkdiv:inst1|clk_2hz elerun:inst3|udsig[2] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "7.180 ns" { clk {} clk~out0 {} clkdiv:inst1|clk_2hz {} elerun:inst3|udsig[2] {} } { 0.000ns 0.000ns 0.560ns 3.505ns } { 0.000ns 1.469ns 0.935ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 7.180 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 7.180 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_16 7 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_16; Fanout = 7; CLK Node = 'clk'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "elevator.bdf" "" { Schematic "E:/project/elevator/elevator.bdf" { { 192 64 232 208 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.560 ns) + CELL(0.935 ns) 2.964 ns clkdiv:inst1\|clk_2hz 2 REG LC_X8_Y6_N4 34 " "Info: 2: + IC(0.560 ns) + CELL(0.935 ns) = 2.964 ns; Loc. = LC_X8_Y6_N4; Fanout = 34; REG Node = 'clkdiv:inst1\|clk_2hz'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.495 ns" { clk clkdiv:inst1|clk_2hz } "NODE_NAME" } } { "clkdiv.vhd" "" { Text "E:/project/elevator/clkdiv.vhd" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.505 ns) + CELL(0.711 ns) 7.180 ns elerun:inst3\|one\[5\] 3 REG LC_X22_Y7_N8 9 " "Info: 3: + IC(3.505 ns) + CELL(0.711 ns) = 7.180 ns; Loc. = LC_X22_Y7_N8; Fanout = 9; REG Node = 'elerun:inst3\|one\[5\]'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.216 ns" { clkdiv:inst1|clk_2hz elerun:inst3|one[5] } "NODE_NAME" } } { "elerun.vhd" "" { Text "E:/project/elevator/elerun.vhd" 213 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.115 ns ( 43.38 % ) " "Info: Total cell delay = 3.115 ns ( 43.38 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.065 ns ( 56.62 % ) " "Info: Total interconnect delay = 4.065 ns ( 56.62 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "7.180 ns" { clk clkdiv:inst1|clk_2hz elerun:inst3|one[5] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "7.180 ns" { clk {} clk~out0 {} clkdiv:inst1|clk_2hz {} elerun:inst3|one[5] {} } { 0.000ns 0.000ns 0.560ns 3.505ns } { 0.000ns 1.469ns 0.935ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "7.180 ns" { clk clkdiv:inst1|clk_2hz elerun:inst3|udsig[2] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "7.180 ns" { clk {} clk~out0 {} clkdiv:inst1|clk_2hz {} elerun:inst3|udsig[2] {} } { 0.000ns 0.000ns 0.560ns 3.505ns } { 0.000ns 1.469ns 0.935ns 0.711ns } "" } } { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "7.180 ns" { clk clkdiv:inst1|clk_2hz elerun:inst3|one[5] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "7.180 ns" { clk {} clk~out0 {} clkdiv:inst1|clk_2hz {} elerun:inst3|one[5] {} } { 0.000ns 0.000ns 0.560ns 3.505ns } { 0.000ns 1.469ns 0.935ns 0.711ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "elerun.vhd" "" { Text "E:/project/elevator/elerun.vhd" 213 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "elerun.vhd" "" { Text "E:/project/elevator/elerun.vhd" 50 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "9.731 ns" { elerun:inst3|one[5] elerun:inst3|LessThan4~269 elerun:inst3|LessThan4~271 elerun:inst3|process0~954 elerun:inst3|process0~963 elerun:inst3|Selector5~187 elerun:inst3|udsig[2]~1014 elerun:inst3|udsig[2]~1016 elerun:inst3|udsig[2] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "9.731 ns" { elerun:inst3|one[5] {} elerun:inst3|LessThan4~269 {} elerun:inst3|LessThan4~271 {} elerun:inst3|process0~954 {} elerun:inst3|process0~963 {} elerun:inst3|Selector5~187 {} elerun:inst3|udsig[2]~1014 {} elerun:inst3|udsig[2]~1016 {} elerun:inst3|udsig[2] {} } { 0.000ns 1.282ns 0.457ns 1.238ns 1.209ns 1.293ns 0.182ns 0.449ns 1.272ns } { 0.000ns 0.442ns 0.292ns 0.114ns 0.114ns 0.114ns 0.114ns 0.292ns 0.867ns } "" } } { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "7.180 ns" { clk clkdiv:inst1|clk_2hz elerun:inst3|udsig[2] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "7.180 ns" { clk {} clk~out0 {} clkdiv:inst1|clk_2hz {} elerun:inst3|udsig[2] {} } { 0.000ns 0.000ns 0.560ns 3.505ns } { 0.000ns 1.469ns 0.935ns 0.711ns } "" } } { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "7.180 ns" { clk clkdiv:inst1|clk_2hz elerun:inst3|one[5] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "7.180 ns" { clk {} clk~out0 {} clkdiv:inst1|clk_2hz {} elerun:inst3|one[5] {} } { 0.000ns 0.000ns 0.560ns 3.505ns } { 0.000ns 1.469ns 0.935ns 0.711ns } "" } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0 "" 0}
{ "Info" "ITDB_TSU_RESULT" "elerun:inst3\|udsig\[2\] alarm clk 5.143 ns register " "Info: tsu for register \"elerun:inst3\|udsig\[2\]\" (data pin = \"alarm\", clock pin = \"clk\") is 5.143 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "12.286 ns + Longest pin register " "Info: + Longest pin to register delay is 12.286 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns alarm 1 PIN PIN_32 2 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_32; Fanout = 2; PIN Node = 'alarm'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { alarm } "NODE_NAME" } } { "elevator.bdf" "" { Schematic "E:/project/elevator/elevator.bdf" { { 192 304 472 208 "alarm" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(6.555 ns) + CELL(0.292 ns) 8.316 ns elerun:inst3\|udsig\[2\]~1010 2 COMB LC_X16_Y6_N2 1 " "Info: 2: + IC(6.555 ns) + CELL(0.292 ns) = 8.316 ns; Loc. = LC_X16_Y6_N2; Fanout = 1; COMB Node = 'elerun:inst3\|udsig\[2\]~1010'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "6.847 ns" { alarm elerun:inst3|udsig[2]~1010 } "NODE_NAME" } } { "elerun.vhd" "" { Text "E:/project/elevator/elerun.vhd" 50 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.093 ns) + CELL(0.442 ns) 9.851 ns elerun:inst3\|udsig\[2\]~1011 3 COMB LC_X19_Y6_N5 2 " "Info: 3: + IC(1.093 ns) + CELL(0.442 ns) = 9.851 ns; Loc. = LC_X19_Y6_N5; Fanout = 2; COMB Node = 'elerun:inst3\|udsig\[2\]~1011'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.535 ns" { elerun:inst3|udsig[2]~1010 elerun:inst3|udsig[2]~1011 } "NODE_NAME" } } { "elerun.vhd" "" { Text "E:/project/elevator/elerun.vhd" 50 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.182 ns) + CELL(0.114 ns) 10.147 ns elerun:inst3\|udsig\[2\]~1016 4 COMB LC_X19_Y6_N6 2 " "Info: 4: + IC(0.182 ns) + CELL(0.114 ns) = 10.147 ns; Loc. = LC_X19_Y6_N6; Fanout = 2; COMB Node = 'elerun:inst3\|udsig\[2\]~1016'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.296 ns" { elerun:inst3|udsig[2]~1011 elerun:inst3|udsig[2]~1016 } "NODE_NAME" } } { "elerun.vhd" "" { Text "E:/project/elevator/elerun.vhd" 50 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.272 ns) + CELL(0.867 ns) 12.286 ns elerun:inst3\|udsig\[2\] 5 REG LC_X20_Y8_N7 1 " "Info: 5: + IC(1.272 ns) + CELL(0.867 ns) = 12.286 ns; Loc. = LC_X20_Y8_N7; Fanout = 1; REG Node = 'elerun:inst3\|udsig\[2\]'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.139 ns" { elerun:inst3|udsig[2]~1016 elerun:inst3|udsig[2] } "NODE_NAME" } } { "elerun.vhd" "" { Text "E:/project/elevator/elerun.vhd" 50 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.184 ns ( 25.92 % ) " "Info: Total cell delay = 3.184 ns ( 25.92 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "9.102 ns ( 74.08 % ) " "Info: Total interconnect delay = 9.102 ns ( 74.08 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "12.286 ns" { alarm elerun:inst3|udsig[2]~1010 elerun:inst3|udsig[2]~1011 elerun:inst3|udsig[2]~1016 elerun:inst3|udsig[2] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "12.286 ns" { alarm {} alarm~out0 {} elerun:inst3|udsig[2]~1010 {} elerun:inst3|udsig[2]~1011 {} elerun:inst3|udsig[2]~1016 {} elerun:inst3|udsig[2] {} } { 0.000ns 0.000ns 6.555ns 1.093ns 0.182ns 1.272ns } { 0.000ns 1.469ns 0.292ns 0.442ns 0.114ns 0.867ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "elerun.vhd" "" { Text "E:/project/elevator/elerun.vhd" 50 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 7.180 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 7.180 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_16 7 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_16; Fanout = 7; CLK Node = 'clk'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "elevator.bdf" "" { Schematic "E:/project/elevator/elevator.bdf" { { 192 64 232 208 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.560 ns) + CELL(0.935 ns) 2.964 ns clkdiv:inst1\|clk_2hz 2 REG LC_X8_Y6_N4 34 " "Info: 2: + IC(0.560 ns) + CELL(0.935 ns) = 2.964 ns; Loc. = LC_X8_Y6_N4; Fanout = 34; REG Node = 'clkdiv:inst1\|clk_2hz'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.495 ns" { clk clkdiv:inst1|clk_2hz } "NODE_NAME" } } { "clkdiv.vhd" "" { Text "E:/project/elevator/clkdiv.vhd" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.505 ns) + CELL(0.711 ns) 7.180 ns elerun:inst3\|udsig\[2\] 3 REG LC_X20_Y8_N7 1 " "Info: 3: + IC(3.505 ns) + CELL(0.711 ns) = 7.180 ns; Loc. = LC_X20_Y8_N7; Fanout = 1; REG Node = 'elerun:inst3\|udsig\[2\]'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.216 ns" { clkdiv:inst1|clk_2hz elerun:inst3|udsig[2] } "NODE_NAME" } } { "elerun.vhd" "" { Text "E:/project/elevator/elerun.vhd" 50 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.115 ns ( 43.38 % ) " "Info: Total cell delay = 3.115 ns ( 43.38 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.065 ns ( 56.62 % ) " "Info: Total interconnect delay = 4.065 ns ( 56.62 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "7.180 ns" { clk clkdiv:inst1|clk_2hz elerun:inst3|udsig[2] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "7.180 ns" { clk {} clk~out0 {} clkdiv:inst1|clk_2hz {} elerun:inst3|udsig[2] {} } { 0.000ns 0.000ns 0.560ns 3.505ns } { 0.000ns 1.469ns 0.935ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "12.286 ns" { alarm elerun:inst3|udsig[2]~1010 elerun:inst3|udsig[2]~1011 elerun:inst3|udsig[2]~1016 elerun:inst3|udsig[2] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "12.286 ns" { alarm {} alarm~out0 {} elerun:inst3|udsig[2]~1010 {} elerun:inst3|udsig[2]~1011 {} elerun:inst3|udsig[2]~1016 {} elerun:inst3|udsig[2] {} } { 0.000ns 0.000ns 6.555ns 1.093ns 0.182ns 1.272ns } { 0.000ns 1.469ns 0.292ns 0.442ns 0.114ns 0.867ns } "" } } { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "7.180 ns" { clk clkdiv:inst1|clk_2hz elerun:inst3|udsig[2] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "7.180 ns" { clk {} clk~out0 {} clkdiv:inst1|clk_2hz {} elerun:inst3|udsig[2] {} } { 0.000ns 0.000ns 0.560ns 3.505ns } { 0.000ns 1.469ns 0.935ns 0.711ns } "" } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk doorlight elerun:inst3\|doorlight 12.919 ns register " "Info: tco from clock \"clk\" to destination pin \"doorlight\" through register \"elerun:inst3\|doorlight\" is 12.919 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 7.180 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 7.180 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_16 7 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_16; Fanout = 7; CLK Node = 'clk'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "elevator.bdf" "" { Schematic "E:/project/elevator/elevator.bdf" { { 192 64 232 208 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.560 ns) + CELL(0.935 ns) 2.964 ns clkdiv:inst1\|clk_2hz 2 REG LC_X8_Y6_N4 34 " "Info: 2: + IC(0.560 ns) + CELL(0.935 ns) = 2.964 ns; Loc. = LC_X8_Y6_N4; Fanout = 34; REG Node = 'clkdiv:inst1\|clk_2hz'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.495 ns" { clk clkdiv:inst1|clk_2hz } "NODE_NAME" } } { "clkdiv.vhd" "" { Text "E:/project/elevator/clkdiv.vhd" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.505 ns) + CELL(0.711 ns) 7.180 ns elerun:inst3\|doorlight 3 REG LC_X16_Y6_N3 2 " "Info: 3: + IC(3.505 ns) + CELL(0.711 ns) = 7.180 ns; Loc. = LC_X16_Y6_N3; Fanout = 2; REG Node = 'elerun:inst3\|doorlight'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.216 ns" { clkdiv:inst1|clk_2hz elerun:inst3|doorlight } "NODE_NAME" } } { "elerun.vhd" "" { Text "E:/project/elevator/elerun.vhd" 24 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.115 ns ( 43.38 % ) " "Info: Total cell delay = 3.115 ns ( 43.38 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.065 ns ( 56.62 % ) " "Info: Total interconnect delay = 4.065 ns ( 56.62 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "7.180 ns" { clk clkdiv:inst1|clk_2hz elerun:inst3|doorlight } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "7.180 ns" { clk {} clk~out0 {} clkdiv:inst1|clk_2hz {} elerun:inst3|doorlight {} } { 0.000ns 0.000ns 0.560ns 3.505ns } { 0.000ns 1.469ns 0.935ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "elerun.vhd" "" { Text "E:/project/elevator/elerun.vhd" 24 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.515 ns + Longest register pin " "Info: + Longest register to pin delay is 5.515 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns elerun:inst3\|doorlight 1 REG LC_X16_Y6_N3 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X16_Y6_N3; Fanout = 2; REG Node = 'elerun:inst3\|doorlight'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { elerun:inst3|doorlight } "NODE_NAME" } } { "elerun.vhd" "" { Text "E:/project/elevator/elerun.vhd" 24 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.391 ns) + CELL(2.124 ns) 5.515 ns doorlight 2 PIN PIN_33 0 " "Info: 2: + IC(3.391 ns) + CELL(2.124 ns) = 5.515 ns; Loc. = PIN_33; Fanout = 0; PIN Node = 'doorlight'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "5.515 ns" { elerun:inst3|doorlight doorlight } "NODE_NAME" } } { "elevator.bdf" "" { Schematic "E:/project/elevator/elevator.bdf" { { 224 768 944 240 "doorlight" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.124 ns ( 38.51 % ) " "Info: Total cell delay = 2.124 ns ( 38.51 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.391 ns ( 61.49 % ) " "Info: Total interconnect delay = 3.391 ns ( 61.49 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "5.515 ns" { elerun:inst3|doorlight doorlight } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "5.515 ns" { elerun:inst3|doorlight {} doorlight {} } { 0.000ns 3.391ns } { 0.000ns 2.124ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "7.180 ns" { clk clkdiv:inst1|clk_2hz elerun:inst3|doorlight } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "7.180 ns" { clk {} clk~out0 {} clkdiv:inst1|clk_2hz {} elerun:inst3|doorlight {} } { 0.000ns 0.000ns 0.560ns 3.505ns } { 0.000ns 1.469ns 0.935ns 0.711ns } "" } } { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "5.515 ns" { elerun:inst3|doorlight doorlight } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "5.515 ns" { elerun:inst3|doorlight {} doorlight {} } { 0.000ns 3.391ns } { 0.000ns 2.124ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0}