prev_cmp_elevator.fit.qmsg

来自「六层电梯控制vhdl六层电梯控制vhdl六层电梯控制vhdl六层电梯控制vhdl」· QMSG 代码 · 共 50 行 · 第 1/4 页

{ "Info" "IFSAC_FSAC_FINISH_LUT_IO_RAM_PACKING" "" "Info: Finished moving registers into I/O cells, LUTs, and RAM blocks" {  } {  } 0 0 "Finished moving registers into I/O cells, LUTs, and RAM blocks" 0 0 "" 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "00:00:00 " "Info: Finished register packing: elapsed time is 00:00:00" {  } {  } 0 0 "Finished register packing: elapsed time is %1!s!" 0 0 "" 0}
{ "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement " "Info: Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement" { { "Info" "IFSAC_FSAC_SINGLE_IOC_GROUP_STATISTICS" "36 unused 3.30 19 17 0 " "Info: Number of I/O pins in group: 36 (unused VREF, 3.30 VCCIO, 19 input, 17 output, 0 bidirectional)" { { "Info" "IFSAC_FSAC_IO_STDS_IN_IOC_GROUP" "3.3-V LVTTL. " "Info: I/O standards used: 3.3-V LVTTL." {  } {  } 0 0 "I/O standards used: %1!s!" 0 0 "" 0}  } {  } 0 0 "Number of I/O pins in group: %1!d! (%2!s! VREF, %3!s! VCCIO, %4!d! input, %5!d! output, %6!d! bidirectional)" 0 0 "" 0}  } {  } 0 0 "Statistics of %1!s!" 0 0 "" 0}
{ "Info" "IFSAC_FSAC_IO_STATS_BEFORE_AFTER_PLACEMENT" "before " "Info: I/O bank details before I/O pin placement" { { "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O banks " "Info: Statistics of I/O banks" { { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "1 does not use undetermined 4 18 " "Info: I/O bank number 1 does not use VREF pins and has undetermined VCCIO pins. 4 total pin(s) used --  18 pins available" {  } {  } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "" 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "2 does not use undetermined 0 28 " "Info: I/O bank number 2 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  28 pins available" {  } {  } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "" 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "3 does not use undetermined 0 26 " "Info: I/O bank number 3 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  26 pins available" {  } {  } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "" 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "4 does not use undetermined 0 28 " "Info: I/O bank number 4 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  28 pins available" {  } {  } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "" 0}  } {  } 0 0 "Statistics of %1!s!" 0 0 "" 0}  } {  } 0 0 "I/O bank details %1!s! I/O pin placement" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Info: Fitter placement preparation operations beginning" {  } {  } 0 0 "Fitter placement preparation operations beginning" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Info: Fitter placement preparation operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Info: Fitter placement operations beginning" {  } {  } 0 0 "Fitter placement operations beginning" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" {  } {  } 0 0 "Fitter placement was successful" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Info: Fitter placement operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "" 0}
{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "8.592 ns register register " "Info: Estimated most critical path is register to register delay of 8.592 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns keypro:inst\|fdnlight\[1\] 1 REG LAB_X24_Y8 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X24_Y8; Fanout = 4; REG Node = 'keypro:inst\|fdnlight\[1\]'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { keypro:inst|fdnlight[1] } "NODE_NAME" } } { "keypro.vhd" "" { Text "E:/project/elevator/keypro.vhd" 35 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.161 ns) + CELL(0.292 ns) 1.453 ns elerun:inst3\|Mux2~218 2 COMB LAB_X24_Y5 1 " "Info: 2: + IC(1.161 ns) + CELL(0.292 ns) = 1.453 ns; Loc. = LAB_X24_Y5; Fanout = 1; COMB Node = 'elerun:inst3\|Mux2~218'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.453 ns" { keypro:inst|fdnlight[1] elerun:inst3|Mux2~218 } "NODE_NAME" } } { "elerun.vhd" "" { Text "E:/project/elevator/elerun.vhd" 160 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.451 ns) + CELL(0.442 ns) 2.346 ns elerun:inst3\|Mux2~219 3 COMB LAB_X25_Y5 4 " "Info: 3: + IC(0.451 ns) + CELL(0.442 ns) = 2.346 ns; Loc. = LAB_X25_Y5; Fanout = 4; COMB Node = 'elerun:inst3\|Mux2~219'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.893 ns" { elerun:inst3|Mux2~218 elerun:inst3|Mux2~219 } "NODE_NAME" } } { "elerun.vhd" "" { Text "E:/project/elevator/elerun.vhd" 160 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.250 ns) + CELL(0.114 ns) 3.710 ns elerun:inst3\|process0~961 4 COMB LAB_X26_Y7 3 " "Info: 4: + IC(1.250 ns) + CELL(0.114 ns) = 3.710 ns; Loc. = LAB_X26_Y7; Fanout = 3; COMB Node = 'elerun:inst3\|process0~961'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.364 ns" { elerun:inst3|Mux2~219 elerun:inst3|process0~961 } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.779 ns) + CELL(0.114 ns) 4.603 ns elerun:inst3\|process0~958 5 COMB LAB_X25_Y7 4 " "Info: 5: + IC(0.779 ns) + CELL(0.114 ns) = 4.603 ns; Loc. = LAB_X25_Y7; Fanout = 4; COMB Node = 'elerun:inst3\|process0~958'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.893 ns" { elerun:inst3|process0~961 elerun:inst3|process0~958 } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.233 ns) + CELL(0.114 ns) 5.950 ns elerun:inst3\|posreg~890 6 COMB LAB_X24_Y8 1 " "Info: 6: + IC(1.233 ns) + CELL(0.114 ns) = 5.950 ns; Loc. = LAB_X24_Y8; Fanout = 1; COMB Node = 'elerun:inst3\|posreg~890'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.347 ns" { elerun:inst3|process0~958 elerun:inst3|posreg~890 } "NODE_NAME" } } { "elerun.vhd" "" { Text "E:/project/elevator/elerun.vhd" 39 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.055 ns) + CELL(0.292 ns) 7.297 ns elerun:inst3\|udsig\[6\]~1012 7 COMB LAB_X24_Y7 1 " "Info: 7: + IC(1.055 ns) + CELL(0.292 ns) = 7.297 ns; Loc. = LAB_X24_Y7; Fanout = 1; COMB Node = 'elerun:inst3\|udsig\[6\]~1012'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.347 ns" { elerun:inst3|posreg~890 elerun:inst3|udsig[6]~1012 } "NODE_NAME" } } { "elerun.vhd" "" { Text "E:/project/elevator/elerun.vhd" 50 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.428 ns) + CELL(0.867 ns) 8.592 ns elerun:inst3\|udsig\[6\] 8 REG LAB_X24_Y7 4 " "Info: 8: + IC(0.428 ns) + CELL(0.867 ns) = 8.592 ns; Loc. = LAB_X24_Y7; Fanout = 4; REG Node = 'elerun:inst3\|udsig\[6\]'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.295 ns" { elerun:inst3|udsig[6]~1012 elerun:inst3|udsig[6] } "NODE_NAME" } } { "elerun.vhd" "" { Text "E:/project/elevator/elerun.vhd" 50 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.235 ns ( 26.01 % ) " "Info: Total cell delay = 2.235 ns ( 26.01 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.357 ns ( 73.99 % ) " "Info: Total interconnect delay = 6.357 ns ( 73.99 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "8.592 ns" { keypro:inst|fdnlight[1] elerun:inst3|Mux2~218 elerun:inst3|Mux2~219 elerun:inst3|process0~961 elerun:inst3|process0~958 elerun:inst3|posreg~890 elerun:inst3|udsig[6]~1012 elerun:inst3|udsig[6] } "NODE_NAME" } }  } 0 0 "Estimated most critical path is %2!s! to %3!s! delay of %1!s!" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" {  } {  } 0 0 "Fitter routing operations beginning" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "1 " "Info: Average interconnect usage is 1% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "3 X14_Y0 X27_Y14 " "Info: Peak interconnect usage is 3% of the available device resources in the region that extends from location X14_Y0 to location X27_Y14" {  } {  } 0 0 "Peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "" 0}  } {  } 0 0 "Average interconnect usage is %1!d!%% of the available device resources" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Info: Fitter routing operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "" 0}