prev_cmp_elevator.tan.qmsg

来自「六层电梯控制vhdl六层电梯控制vhdl六层电梯控制vhdl六层电梯控制vhdl」· QMSG 代码 · 共 11 行 · 第 1/3 页

{ "Info" "ITDB_TH_RESULT" "elerun:inst3\|doorlight reset clk 3.487 ns register " "Info: th for register \"elerun:inst3\|doorlight\" (data pin = \"reset\", clock pin = \"clk\") is 3.487 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 7.573 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 7.573 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_17 7 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_17; Fanout = 7; CLK Node = 'clk'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "elevator.bdf" "" { Schematic "E:/project/elevator/elevator.bdf" { { 192 64 232 208 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.560 ns) + CELL(0.935 ns) 2.964 ns clkdiv:inst1\|clk_2hz 2 REG LC_X11_Y6_N5 34 " "Info: 2: + IC(0.560 ns) + CELL(0.935 ns) = 2.964 ns; Loc. = LC_X11_Y6_N5; Fanout = 34; REG Node = 'clkdiv:inst1\|clk_2hz'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.495 ns" { clk clkdiv:inst1|clk_2hz } "NODE_NAME" } } { "clkdiv.vhd" "" { Text "E:/project/elevator/clkdiv.vhd" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.898 ns) + CELL(0.711 ns) 7.573 ns elerun:inst3\|doorlight 3 REG LC_X22_Y7_N0 2 " "Info: 3: + IC(3.898 ns) + CELL(0.711 ns) = 7.573 ns; Loc. = LC_X22_Y7_N0; Fanout = 2; REG Node = 'elerun:inst3\|doorlight'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.609 ns" { clkdiv:inst1|clk_2hz elerun:inst3|doorlight } "NODE_NAME" } } { "elerun.vhd" "" { Text "E:/project/elevator/elerun.vhd" 24 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.115 ns ( 41.13 % ) " "Info: Total cell delay = 3.115 ns ( 41.13 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.458 ns ( 58.87 % ) " "Info: Total interconnect delay = 4.458 ns ( 58.87 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "7.573 ns" { clk clkdiv:inst1|clk_2hz elerun:inst3|doorlight } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "7.573 ns" { clk {} clk~out0 {} clkdiv:inst1|clk_2hz {} elerun:inst3|doorlight {} } { 0.000ns 0.000ns 0.560ns 3.898ns } { 0.000ns 1.469ns 0.935ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TH_DELAY" "0.015 ns + " "Info: + Micro hold delay of destination is 0.015 ns" {  } { { "elerun.vhd" "" { Text "E:/project/elevator/elerun.vhd" 24 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.101 ns - Shortest pin register " "Info: - Shortest pin to register delay is 4.101 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns reset 1 PIN PIN_16 18 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_16; Fanout = 18; PIN Node = 'reset'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { reset } "NODE_NAME" } } { "elevator.bdf" "" { Schematic "E:/project/elevator/elevator.bdf" { { 272 64 232 288 "reset" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.190 ns) + CELL(0.114 ns) 2.773 ns elerun:inst3\|process0~0 2 COMB LC_X22_Y7_N4 18 " "Info: 2: + IC(1.190 ns) + CELL(0.114 ns) = 2.773 ns; Loc. = LC_X22_Y7_N4; Fanout = 18; COMB Node = 'elerun:inst3\|process0~0'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.304 ns" { reset elerun:inst3|process0~0 } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.461 ns) + CELL(0.867 ns) 4.101 ns elerun:inst3\|doorlight 3 REG LC_X22_Y7_N0 2 " "Info: 3: + IC(0.461 ns) + CELL(0.867 ns) = 4.101 ns; Loc. = LC_X22_Y7_N0; Fanout = 2; REG Node = 'elerun:inst3\|doorlight'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.328 ns" { elerun:inst3|process0~0 elerun:inst3|doorlight } "NODE_NAME" } } { "elerun.vhd" "" { Text "E:/project/elevator/elerun.vhd" 24 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.450 ns ( 59.74 % ) " "Info: Total cell delay = 2.450 ns ( 59.74 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.651 ns ( 40.26 % ) " "Info: Total interconnect delay = 1.651 ns ( 40.26 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.101 ns" { reset elerun:inst3|process0~0 elerun:inst3|doorlight } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "4.101 ns" { reset {} reset~out0 {} elerun:inst3|process0~0 {} elerun:inst3|doorlight {} } { 0.000ns 0.000ns 1.190ns 0.461ns } { 0.000ns 1.469ns 0.114ns 0.867ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "7.573 ns" { clk clkdiv:inst1|clk_2hz elerun:inst3|doorlight } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "7.573 ns" { clk {} clk~out0 {} clkdiv:inst1|clk_2hz {} elerun:inst3|doorlight {} } { 0.000ns 0.000ns 0.560ns 3.898ns } { 0.000ns 1.469ns 0.935ns 0.711ns } "" } } { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.101 ns" { reset elerun:inst3|process0~0 elerun:inst3|doorlight } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "4.101 ns" { reset {} reset~out0 {} elerun:inst3|process0~0 {} elerun:inst3|doorlight {} } { 0.000ns 0.000ns 1.190ns 0.461ns } { 0.000ns 1.469ns 0.114ns 0.867ns } "" } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 2 s Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "115 " "Info: Allocated 115 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Sun Dec 28 15:34:11 2008 " "Info: Processing ended: Sun Dec 28 15:34:11 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}