prev_cmp_elevator.qmsg

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{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Extra Info: Performing register packing on registers with non-logic cell location assignments" {  } {  } 1 0 "Performing register packing on registers with non-logic cell location assignments" 1 0 "" 0}
{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Extra Info: Completed register packing on registers with non-logic cell location assignments" {  } {  } 1 0 "Completed register packing on registers with non-logic cell location assignments" 1 0 "" 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "User Assigned Global Signals Promotion Operation " "Info: Completed User Assigned Global Signals Promotion Operation" {  } {  } 0 0 "Completed %1!s!" 0 0 "" 0}
{ "Info" "IFYGR_FYGR_GLOBAL_LINES_NEEDED_FOR_TORNADO_DQS" "0 " "Info: DQS I/O pins require 0 global routing resources" {  } {  } 0 0 "DQS I/O pins require %1!d! global routing resources" 0 0 "" 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "clk Global clock in PIN 17 " "Info: Automatically promoted signal \"clk\" to use Global clock in PIN 17" {  } { { "elevator.bdf" "" { Schematic "E:/project/elevator/elevator.bdf" { { 192 64 232 208 "clk" "" } } } }  } 0 0 "Automatically promoted signal \"%1!s!\" to use %2!s!" 0 0 "" 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "clkdiv:inst1\|clk_2hz Global clock " "Info: Automatically promoted signal \"clkdiv:inst1\|clk_2hz\" to use Global clock" {  } { { "clkdiv.vhd" "" { Text "E:/project/elevator/clkdiv.vhd" 9 -1 0 } }  } 0 0 "Automatically promoted signal \"%1!s!\" to use %2!s!" 0 0 "" 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "clkdiv:inst1\|clk_8hz Global clock " "Info: Automatically promoted signal \"clkdiv:inst1\|clk_8hz\" to use Global clock" {  } { { "clkdiv.vhd" "" { Text "E:/project/elevator/clkdiv.vhd" 10 -1 0 } }  } 0 0 "Automatically promoted signal \"%1!s!\" to use %2!s!" 0 0 "" 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "reset Global clock in PIN 16 " "Info: Automatically promoted some destinations of signal \"reset\" to use Global clock in PIN 16" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "elerun:inst3\|process0~0 " "Info: Destination \"elerun:inst3\|process0~0\" may be non-global or may not use global clock" {  } {  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "" 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "elerun:inst3\|udsig\[2\]~1010 " "Info: Destination \"elerun:inst3\|udsig\[2\]~1010\" may be non-global or may not use global clock" {  } { { "elerun.vhd" "" { Text "E:/project/elevator/elerun.vhd" 50 -1 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "" 0}  } { { "elevator.bdf" "" { Schematic "E:/project/elevator/elevator.bdf" { { 272 64 232 288 "reset" "" } } } }  } 0 0 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0 "" 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "elerun:inst3\|process0~0 Global clock " "Info: Automatically promoted some destinations of signal \"elerun:inst3\|process0~0\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "elerun:inst3\|doorlight " "Info: Destination \"elerun:inst3\|doorlight\" may be non-global or may not use global clock" {  } { { "elerun.vhd" "" { Text "E:/project/elevator/elerun.vhd" 24 -1 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "" 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "elerun:inst3\|posreg\[0\] " "Info: Destination \"elerun:inst3\|posreg\[0\]\" may be non-global or may not use global clock" {  } { { "elerun.vhd" "" { Text "E:/project/elevator/elerun.vhd" 50 -1 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "" 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "elerun:inst3\|posreg\[2\]~895 " "Info: Destination \"elerun:inst3\|posreg\[2\]~895\" may be non-global or may not use global clock" {  } { { "elerun.vhd" "" { Text "E:/project/elevator/elerun.vhd" 50 -1 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "" 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "elerun:inst3\|udflag " "Info: Destination \"elerun:inst3\|udflag\" may be non-global or may not use global clock" {  } { { "elerun.vhd" "" { Text "E:/project/elevator/elerun.vhd" 38 -1 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { elerun:inst3|process0~0 } "NODE_NAME" } } { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { elerun:inst3|process0~0 } "NODE_NAME" } }  } 0 0 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0 "" 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Global Promotion Operation " "Info: Completed Auto Global Promotion Operation" {  } {  } 0 0 "Completed %1!s!" 0 0 "" 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_FYGR_REGPACKING_INFO" "" "Info: Starting register packing" {  } {  } 0 0 "Starting register packing" 0 0 "" 0}
{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Extra Info: Started Fast Input/Output/OE register processing" {  } {  } 1 0 "Started Fast Input/Output/OE register processing" 1 0 "" 0}
{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Extra Info: Finished Fast Input/Output/OE register processing" {  } {  } 1 0 "Finished Fast Input/Output/OE register processing" 1 0 "" 0}