main_module.v

AES算法的verilog代码

module  all(all_rin,all_rout,all_kin,all_kout,clk); //AES??????
input     [127:0]   all_rin;
input     [127:0]   all_kin;
input               clk;
output    [127:0]   all_rout;
output    [127:0]   all_kout;
reg       [127:0]   all_rout;
reg       [127:0]   all_kout;
wire      [127:0]   rud_out0;
wire      [127:0]   rud_out1;
wire      [127:0]   rud_out2;
wire      [127:0]   rud_out3;
wire      [127:0]   rud_out4;
wire      [127:0]   rud_out5;
wire      [127:0]   rud_out6;
wire      [127:0]   rud_out7;
wire      [127:0]   rud_out8;
wire      [127:0]   rud_out9;
wire      [127:0]   rud_out10;
wire      [127:0]   kud_out0;
wire      [127:0]   kud_out1;
wire      [127:0]   kud_out2;
wire      [127:0]   kud_out3;
wire      [127:0]   kud_out4;
wire      [127:0]   kud_out5;
wire      [127:0]   kud_out6;
wire      [127:0]   kud_out7;
wire      [127:0]   kud_out8;
wire      [127:0]   kud_out9;
wire      [127:0]   kud_out10;
roundkey0  rud0(.rin0(all_rin), .rout_0(rud_out0), .kin0(all_kin), .kout_0(kud_out0), .clk(clk));  // ????????
roundkey1  rud1(.rin1(rud_out0), .rout_1(rud_out1), .kin1(kud_out0), .kout_1(kud_out1), .clk(clk));
roundkey2  rud2(.rin2(rud_out1), .rout_2(rud_out2), .kin2(kud_out1), .kout_2(kud_out2), .clk(clk));
roundkey3  rud3(.rin3(rud_out2), .rout_3(rud_out3), .kin3(kud_out2), .kout_3(kud_out3), .clk(clk));
roundkey4  rud4(.rin4(rud_out3), .rout_4(rud_out4), .kin4(kud_out3), .kout_4(kud_out4), .clk(clk));
roundkey5  rud5(.rin5(rud_out4), .rout_5(rud_out5), .kin5(kud_out4), .kout_5(kud_out5), .clk(clk));
roundkey6  rud6(.rin6(rud_out5), .rout_6(rud_out6), .kin6(kud_out5), .kout_6(kud_out6), .clk(clk));
roundkey7  rud7(.rin7(rud_out6), .rout_7(rud_out7), .kin7(kud_out6), .kout_7(kud_out7), .clk(clk));
roundkey8  rud8(.rin8(rud_out7), .rout_8(rud_out8), .kin8(kud_out7), .kout_8(kud_out8), .clk(clk));
roundkey9  rud9(.rin9(rud_out8), .rout_9(rud_out9), .kin9(kud_out8), .kout_9(kud_out9), .clk(clk));
roundkey10  rud10(.rin10(rud_out9), .rout_10(rud_out10), .kin10(kud_out9), .kout_10(kud_out10), .clk(clk));
always @ (posedge clk)
  begin
    all_rout<=rud_out10;
	 all_kout<=kud_out10;
  end
endmodule