module_round.v

AES算法的verilog代码

module   round(rin,rout,clk);  //?????????
input    [127:0]        rin;
output   [127:0]        rout;
input                   clk;
reg      [127:0]        rout;
reg      [7:0]          rin_0;
reg      [7:0]          rin_1;
reg      [7:0]          rin_2;
reg      [7:0]          rin_3;
reg      [7:0]          rin_4;
reg      [7:0]          rin_5;
reg      [7:0]          rin_6;
reg      [7:0]          rin_7;
reg      [7:0]          rin_8;
reg      [7:0]          rin_9;
reg      [7:0]          rin_10;
reg      [7:0]          rin_11;
reg      [7:0]          rin_12;
reg      [7:0]          rin_13;
reg      [7:0]          rin_14;
reg      [7:0]          rin_15;
wire     [31:0]         rout1;
wire     [31:0]         rout2;
wire     [31:0]         rout3;
wire     [31:0]         rout4;

always  @  (posedge clk)
    begin 
		rin_0<=rin[127:120];
		rin_1<=rin[119:112];
		rin_2<=rin[111:104];
		rin_3<=rin[103:96];
		rin_4<=rin[95:88];
		rin_5<=rin[87:80];
		rin_6<=rin[79:72];
		rin_7<=rin[71:64];
		rin_8<=rin[63:56];
		rin_9<=rin[55:48];
		rin_10<=rin[47:40];
		rin_11<=rin[39:32];
		rin_12<=rin[31:24];
		rin_13<=rin[23:16];
		rin_14<=rin[15:8];
		rin_15<=rin[7:0];
	end
 cloum   clm1(.cin1(rin_0), .cin2(rin_5), .cin3(rin_10), .cin4(rin_15), .clk(clk), .cout(rout1));
 cloum   clm2(.cin1(rin_4), .cin2(rin_9), .cin3(rin_14), .cin4(rin_3), .clk(clk), .cout(rout2));
 cloum   clm3(.cin1(rin_8), .cin2(rin_13), .cin3(rin_2), .cin4(rin_7), .clk(clk), .cout(rout3));
 cloum   clm4(.cin1(rin_12), .cin2(rin_1), .cin3(rin_6), .cin4(rin_11), .clk(clk), .cout(rout4));
always  @  (posedge clk)
	begin
		rout[127:96]<=rout1;
		rout[95:64]<=rout2;
		rout[63:32]<=rout3;
		rout[31:0]<=rout4;
	end
endmodule