module_cloum.v

AES算法的verilog代码

module  cloum(cin1,cin2,cin3,cin4,clk,cout); //?????
input    [7:0]      cin1;
input    [7:0]      cin2;
input    [7:0]      cin3;
input    [7:0]      cin4;
input               clk;
output   [31:0]     cout;
reg      [31:0]     cout;
wire     [31:0]     cout1_w;
wire     [31:0]     cout2_w;
wire     [31:0]     cout3_w;
wire     [31:0]     cout4_w;
reg      [31:0]     cout1_r;
reg      [31:0]     cout2_r;
reg      [31:0]     cout3_r;
reg      [31:0]     cout4_r;
    box  c1(.din(cin1),  .dout(cout1_w),  .clk(clk));
	 box  c2(.din(cin2),  .dout(cout2_w),  .clk(clk));
	 box  c3(.din(cin3),  .dout(cout3_w),  .clk(clk));
	 box  c4(.din(cin4),  .dout(cout4_w),  .clk(clk));
always  @ (posedge clk)
     begin
	  cout1_r<=cout1_w;
     cout2_r[23:0]<=cout2_w[31:8];
	  cout2_r[31:24]<=cout2_w[7:0];
	  cout3_r[31:16]<=cout3_w[15:0];
	  cout3_r[15:0]<=cout3_w[31:16];
     cout4_r[31:8]<=cout4_w[23:0];
     cout4_r[7:0]<=cout4_w[31:24];
     cout<=cout1_r^cout2_r^cout3_r^cout4_r;
	 end
	 endmodule