module_roundkey10.v

来自「AES算法的verilog代码」· Verilog 代码 · 共 18 行

module roundkey10(rin10,kin10,rout_10,kout_10,clk); // ???????
input    [127:0]    rin10;
input    [127:0]    kin10;
input               clk;
output   [127:0]    rout_10;
output   [127:0]    kout_10;
wire     [127:0]    rout10;
wire     [127:0]    kout10;
reg      [127:0]    rout_10;
reg      [127:0]    kout_10;
round10     rd10(.rin_10(rin10), .rout(rout10), .clk(clk));
keyexp10   kp10(.kin(kin10), .kout(kout10), .clk(clk));
always @ (posedge clk)
   begin
    rout_10<=rout10^kout10;
	kout_10<=kout10;
	end
endmodule