module_roundkey6.v

来自「AES算法的verilog代码」· Verilog 代码 · 共 18 行

module roundkey6(rin6,kin6,rout_6,kout_6,clk); // ???????
input    [127:0]    rin6;
input    [127:0]    kin6;
input               clk;
output   [127:0]    rout_6;
output   [127:0]    kout_6;
wire     [127:0]    rout6;
wire     [127:0]    kout6;
reg      [127:0]    rout_6;
reg      [127:0]    kout_6;
round     rd6(.rin(rin6), .rout(rout6), .clk(clk));
keyexp6   kp6(.kin(kin6), .kout(kout6), .clk(clk));
always @ (posedge clk)
    begin
    rout_6<=rout6^kout6;
	 kout_6<=kout6;
	 end
endmodule