module_roundkey0.v

来自「AES算法的verilog代码」· Verilog 代码 · 共 14 行

module  roundkey0(rin0,kin0,rout_0,kout_0,clk); // ???????????
input    [127:0]    rin0;
input    [127:0]    kin0;
input               clk;
output   [127:0]    rout_0;
output   [127:0]    kout_0;
reg      [127:0]    rout_0;
reg      [127:0]    kout_0;
always @ (posedge clk)
   begin
   rout_0<=rin0^kin0;
   kout_0<=kin0;
   end
endmodule