module_roundkey3.v

来自「AES算法的verilog代码」· Verilog 代码 · 共 18 行

module roundkey3(rin3,kin3,rout_3,kout_3,clk); // ???????
input    [127:0]    rin3;
input    [127:0]    kin3;
input               clk;
output   [127:0]    rout_3;
output   [127:0]    kout_3;
wire     [127:0]    rout3;
wire     [127:0]    kout3;
reg      [127:0]    rout_3;
reg      [127:0]    kout_3;
round     rd3(.rin(rin3), .rout(rout3), .clk(clk));
keyexp3   kp3(.kin(kin3), .kout(kout3), .clk(clk));
always @ (posedge clk)
   begin
    rout_3<=rout3^kout3;
	 kout_3<=kout3;
	end
endmodule