module_round10.v

AES算法的verilog代码

module   round10(rin_10,rout,clk);     //?????????
input    [127:0]      rin_10;
input                 clk;
output   [127:0]      rout;
reg      [127:0]      rout;
reg      [7:0]        rin_10_0;
reg      [7:0]        rin_10_1;
reg      [7:0]        rin_10_2;
reg      [7:0]        rin_10_3;
reg      [7:0]        rin_10_4;
reg      [7:0]        rin_10_5;
reg      [7:0]        rin_10_6;
reg      [7:0]        rin_10_7;
reg      [7:0]        rin_10_8;
reg      [7:0]        rin_10_9;
reg      [7:0]        rin_10_10;
reg      [7:0]        rin_10_11;
reg      [7:0]        rin_10_12;
reg      [7:0]        rin_10_13;
reg      [7:0]        rin_10_14;
reg      [7:0]        rin_10_15;
wire     [7:0]        rout_10_0;
wire     [7:0]        rout_10_1;
wire     [7:0]        rout_10_2;
wire     [7:0]        rout_10_3;
wire     [7:0]        rout_10_4;
wire     [7:0]        rout_10_5;
wire     [7:0]        rout_10_6;
wire     [7:0]        rout_10_7;
wire     [7:0]        rout_10_8;
wire     [7:0]        rout_10_9;
wire     [7:0]        rout_10_10;
wire     [7:0]        rout_10_11;
wire     [7:0]        rout_10_12;
wire     [7:0]        rout_10_13;
wire     [7:0]        rout_10_14;
wire     [7:0]        rout_10_15;
always  @ (posedge  clk)
  begin
      rin_10_0<=rin_10[127:120];
      rin_10_1<=rin_10[119:112];
      rin_10_2<=rin_10[111:104];
      rin_10_3<=rin_10[103:96];
      rin_10_4<=rin_10[95:88];
      rin_10_5<=rin_10[87:80];
      rin_10_6<=rin_10[79:72];
      rin_10_7<=rin_10[71:64];
      rin_10_8<=rin_10[63:56];
      rin_10_9<=rin_10[55:48];
      rin_10_10<=rin_10[47:40];
      rin_10_11<=rin_10[39:32];
      rin_10_12<=rin_10[31:24];
      rin_10_13<=rin_10[23:16];
      rin_10_14<=rin_10[15:8];
      rin_10_15<=rin_10[7:0];
  end
  box10   b0(.din10(rin_10_0), .dout10(rout_10_0), .clk(clk));
  box10   b1(.din10(rin_10_1), .dout10(rout_10_1), .clk(clk));
  box10   b2(.din10(rin_10_2), .dout10(rout_10_2), .clk(clk));
  box10   b3(.din10(rin_10_3), .dout10(rout_10_3), .clk(clk));
  box10   b4(.din10(rin_10_4), .dout10(rout_10_4), .clk(clk));
  box10   b5(.din10(rin_10_5), .dout10(rout_10_5), .clk(clk));
  box10   b6(.din10(rin_10_6), .dout10(rout_10_6), .clk(clk));
  box10   b7(.din10(rin_10_7), .dout10(rout_10_7), .clk(clk));
  box10   b8(.din10(rin_10_8), .dout10(rout_10_8), .clk(clk));
  box10   b9(.din10(rin_10_9), .dout10(rout_10_9), .clk(clk));
  box10   b10(.din10(rin_10_10), .dout10(rout_10_10), .clk(clk));
  box10   b11(.din10(rin_10_11), .dout10(rout_10_11), .clk(clk));
  box10   b12(.din10(rin_10_12), .dout10(rout_10_12), .clk(clk));
  box10   b13(.din10(rin_10_13), .dout10(rout_10_13), .clk(clk));
  box10   b14(.din10(rin_10_14), .dout10(rout_10_14), .clk(clk));
  box10   b15(.din10(rin_10_15), .dout10(rout_10_15), .clk(clk));
always @ (posedge clk)
    begin
      rout[127:120]<=rout_10_0;
      rout[119:112]<=rout_10_5;
      rout[111:104]<=rout_10_10;
      rout[103:96]<=rout_10_15;
      rout[95:88]<=rout_10_4;
      rout[87:80]<=rout_10_9;
      rout[79:72]<=rout_10_14;
      rout[71:64]<=rout_10_3;
      rout[63:56]<=rout_10_8;
      rout[55:48]<=rout_10_13;
      rout[47:40]<=rout_10_2;
      rout[39:32]<=rout_10_7;
      rout[31:24]<=rout_10_12;
      rout[23:16]<=rout_10_1;
      rout[15:8]<=rout_10_6;
      rout[7:0]<=rout_10_11;
    end
endmodule